參數(shù)資料
型號: TH58NVG1S3AFT05
廠商: Toshiba Corporation
英文描述: TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
中文描述: 東芝馬鞍山數(shù)字集成電路硅柵CMOS
文件頁數(shù): 18/32頁
文件大?。?/td> 368K
代理商: TH58NVG1S3AFT05
2003-05-19A
18/32
TH58NVG1S3AFT05
DEVICE OPERATION
Read Mode
Read mode is set when "00H" and “30H” commands are issued to the Command register. Between the
commands, start address for the Read mode need to be issued. Refer to Figure 3 below for sequence and the
block diagram (Refer to the detailed timing chart.).
Random Column Address Change in Read Cycle
RE
BY
/
RY
Start-address input
BY
/
RY
WE
CLE
RE
00H
CE
ALE
I/O
Busy
30H
Page Address N
Column Address M
M
M+1
M+2
Page Address N
WE
CLE
00H
CE
ALE
I/O
Col. M
Page N
Busy
Page N
30H
05H
E0H
Col. M’
M
M+1 M+2 M+3
M’ M’+1 M’+2 M’+3M’+4
Page N
Col. M
Start from Col. M
Start from Col. M’
Start-address input
Cell array
Select page
N
M
Figure 3. Read mode (1) operation
2111
A data transfer operation from the cell array to the register
starts on the rising edge of WE in the 30h command input cycle
(after the address information has been latched). The device will
be in Busy state during this transfer period.
After the transfer period the device returns to Ready state.
Serial data can be output synchronously with the RE clock from
the start address designated in the address input cycle.
Figure 4. Random Column Address Change in Serial Read
Cell array
Select page
N
M
M’
In the serial data out from the register, the column address
can be changed by inputting the column address with 05h and
E0h commands.
The data are read out in serial from the column address which
is input to the device by 05h and E0h commands with /RE clock.
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