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參數(shù)資料
| 型號： | TH7834CCC-RB |
| 廠商： | ATMEL CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Very Highresolution Linear CCD Image Sensor (12000 Pixels) |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, CDIP56 |
| 封裝： | 0.600 INCH, WINDOWED, DIP-56 |
| 文件頁數(shù)： | 6/13頁 |
| 文件大小： | 180K |
| 代理商： | TH7834CCC-RB |
6
TH7834C
1997A–IMAGE–05/02
Operating
Precautions
Shorting the video outputs to VSS or VDD, even temporarily, can permanently damage
the output amplifiers.
Operating Conditions (T = 25°C)
Note:
If no exposure time control is required,
Φ
A1-2
and
Φ
A3-4
must be connected to an adjustable DC bias (see Figure 7).
Typical current in V
DR
, V
A
< 10 μA; in V
GS
, V
ST
< 1 μA.
Timing Diagram
Figure 3.
Line Timing Diagram
Minimum exposure time: Ti min = readout time.
For data rate of 5 MHz: Ti min =
Note:
It is better to clean the shift registers (with running clocks) and not to stop clocking them
after readout time.
= 608.6 μs.
Table 1.
DC Characteristics
Parameter
Symbol
Value
Unit
Min.
Typ.
Max.
Output Amplifier Drain Supply
V
DD1-2
, V
DD3-4
14.5
15
15.5
V
Substrate Voltage
V
SS
0
0
V
Reset DC Bias
V
DR1
, V
DR2
, V
DR3
, V
DR4
V
DD
- 0.5
V
Output Amplifier Source Bias
V
S1
, V
S2
, V
S3
, V
S4
0
V
Output Gate DC Bias
V
GS1-2
, V
GS3-4
2.2
2.4
2.6
V
Photosensitive Zone DC Bias
V
ST
3.5
4
4.5
V
Antiblooming Diode Bias
VA
1-2
, VA
3-4
14
14.5
15
V
Φ
P3-4
Φ
P1-2
Φ
Φ
LS1-2,
LS3-4
Φ
Φ
R1-2,
R3-4
Φ
Ec1
(clamp)
External
Φ
Ech
(Sampling)
Detailed timing diagram
for transfert from
photosite to register
(see fig. 4)
Detailed pixel
timing diagram
(see fig. 5)
Φ
Φ
L1,
L2
Readout time for line M
Cleaning
Pixel N
Integration time Ti for line M+1
-----------------
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