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參數(shù)資料
| 型號： | TH7834CCC-RB |
| 廠商： | ATMEL CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Very Highresolution Linear CCD Image Sensor (12000 Pixels) |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, CDIP56 |
| 封裝： | 0.600 INCH, WINDOWED, DIP-56 |
| 文件頁數(shù)： | 8/13頁 |
| 文件大?。?/td> | 180K |
| 代理商： | TH7834CCC-RB |
8
TH7834C
1997A–IMAGE–05/02
Cross over of complementary clocks (
Φ
L1
and
Φ
L2
) preferably at 50% of their amplitude.
Note:
Generally, the difference between the floating diode level and signal level is the sum of
several signals:
Register clock feedthrough
Average CCD register dark signal proportional to CCD clock period, mode, temperature
Pixel dark signal (depending upon temperature and exposure time)
Pixel signal under illumination
Note:
1. Transients under 0.0V in the clock pulses will lead to charge injection, causing a localized increase of the dark signal. If such
spurious negative transients are present, they can be removed by inserting a serial resistor of appropriate value (typically
20
to 100
) at the relevant driver output.
Table 2.
Elements
Inactive
Prescan
Dark
References
Isolation
Elements
Non Useful
Pixels
Useful Pixels
Signals
Register Clock Feedthrough
X
X
X
X
X
Average CCD Register Dark Signal
X
X
X
X
X
Pixel Dark Signal
X
X
X
Pixel Signal Under Illumination
X
X
Table 3.
Drive Clock Voltage Swings
Parameter
Symbol
Logic
Value
Unit
Min.
Typ.
Max.
Register Main Transport Clock
(1)
Φ
L1
,
Φ
L2
High
8.5
9
11
V
Low
0
0.4
0.6
V
Register End Transport Clock
(1)
Φ
LS1-2
,
Φ
LS3-4
High
8.5
9
11
V
Low
0
0.2
0.4
V
Antiblooming (Low Level) And
Exposure Time Control (High Level)
(1)
Φ
A1-2
,
Φ
A3-4
High
9.5
10
10.5
V
Low
0
To be
adjusted
V
Reset Clock
(1)
Φ
R1-2
,
Φ
R3-4
High
10.5
11
12.5
V
Low
0
1.5
2
V
Transfer Clock
(1)
Φ
P1-2
,
Φ
P3-4
High
10.5
11
11.5
V
Low
0
0.4
0.6
V
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