參數(shù)資料
型號(hào)： THMC50SSOPDBQ
廠商： Texas Instruments, Inc.
英文描述： KPT 55C 55#20 SKT RECP
中文描述： 遠(yuǎn)程/本地溫度監(jiān)視器和通風(fēng)機(jī)的SMBus接口控制器
文件頁(yè)數(shù)： 3/32頁(yè)
文件大?。?/td> 437K
代理商： THMC50SSOPDBQ
THMC50
REMOTE/LOCAL TEMPERATURE MONITOR AND
FAN CONTROLLER WITH SMBus INTERFACE
SLIS090 – JULY 1999
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
13
ADD/NTEST_OUT
Digital I/O
This terminal is used to determine the two LSBs of the SMBus address during initial
power on and it also functions as a digital output when doing a NAND tree test.
AUXRST
3
Digital I/O
(open drain)
This terminal is asserted low while VCC3AUX remains below the reset threshold. It
remains asserted for the reset timeout period after the reset condition is terminated. It is
bidirectional so that the THMC50 can be optionally reset; external logic must be used to
prevent a system auxiliary reset from occurring.
FAN_OFF
1
Digital output
(open drain)
Fan off request output. When commanded low via bit 5 in the configuration register
(0
×
40), this indicates a request to shut the fan off independent of the FAN_SPD output.
When commanded high via bit 5 in the configuration register (0
×
40), it indicates that the
fan may be turned on. This is an open-drain output requiring an external pullup.
Note: This terminal requires external circuitry to turn the fan off. It does not command the
analog output to 0
×
00 (see Typical Application Schematic).
FAN_SPD/NTEST_IN
8
Analog
output/test input
This terminal is an active-high input that enables NAND tree board-level connectivity
testing during device power up. Refer to the section on NAND tree testing. Also used as
the analog output of the 8-bit DAC for fan speed control when not in NAND tree test
mode.
GND
4
Ground
GPI
12
Digital input
General-purpose input. The logic state of this terminal is reflected in bit 4 of the interrupt
status register (0x41). The logic state of the GPI terminal reported in bit 4 of the interrupt
status register (0x41) is inverted from the actual GPI logic state if bit 6 of the configuration
register (0x40) is set to a 1. If bit 6 of the configuration register (0
×
40) is set to a 0, then bit
4 of the interrupt status register (0
×
41) reports the same logic state present on the GPI
terminal.
INT
14
Digital output
(open drain)
System interrupt output. This signal indicates a violation of a set trip point. The INT output
is enabled when bit 1 of the configuration register (0x40) is set to 1. The default state is
disabled.
MR
2
Digital input
Manual reset. A logic low on this input causes RST to be asserted. Once this input is
negated, RST remains asserted for approximately 180 ms. This input has an internal
20-k
pullup resistor. Leave unconnected if not used.
REMOTE_DIODE–
9
Remote thermal
diode negative
input
This is the negative input (current sink) from the remote thermal diode.
REMOTE_DIODE+
10
Remote thermal
diode positive
input
This is the positive input (current source) from the remote thermal diode.
RST
7
Digital output
(open drain)
This terminal is asserted low under any of the following conditions:
VCC3 remains below the reset threshold
While MR is held low
While AUXRST is asserted
It remains asserted for the reset timeout period after the reset conditions are terminated.
The RST function also resets the FAN_SPD analog output to 0xoo when asserted,
unless THERM is asserted, then the FAN_SPD analog output will be 0xFF.
SCL
15
Digital input
Serial SMBus clock
SDA
16
Digital I/O
(open drain)
Serial SMBus bidirectional data
THERM
11
Digital I/O
(open drain)
This is an active low thermal overload output that indicates a violation of a temperature
set point (overtemperature) for at least three monitoring cycles. Also acts as an input to
indicate a thermal event for fan control. When this signal is asserted low externally, a
status bit is set. The automatic fan control is activated to full on whenever this signal is
low.
VCC3
6
Analog input
This is a 3.3-V main voltage monitor input for main reset generator (RST). This is not the
power supply terminal for THMC50.
VCC3AUX
5
Power supply
voltage input
This 3.3-V auxiliary voltage is the THMC50 power source and voltage monitor input for
auxiliary reset generator (AUXRST). This terminal powers all THMC50 internal circuitry.
相關(guān)PDF資料
PDF描述
THMR1E16-6 134，217，728-Word（256MBytes) by 18-Bit(128M-Word × 18Bit) Direct Rambus DRAM Module(I/O Frequency:600MHz）(256M字節(jié)(128M字× 18位)直接Rambus 動(dòng)態(tài)RAM模塊(I/O 頻率:600MHz）)
THMR1E16-7 134，217，728-Word（256MBytes) by 18-Bit(128M-Word × 18Bit) Direct Rambus DRAM Module(I/O Frequency:711MHz）(256M字節(jié)(128M字× 18位)直接Rambus 動(dòng)態(tài)RAM模塊(I/O 頻率:711MHz）)
THMR1E16-8 134，217，728-Word（256MBytes) by 18-Bit(128M-Word × 18Bit) Direct Rambus DRAM Module(I/O Frequency:800MHz）(256M字節(jié)(128M字× 18位)直接Rambus 動(dòng)態(tài)RAM模塊(I/O 頻率:800MHz）)
THMR1E4-6 33,554,432-Word（64MBytes) by 18-Bit(32M-Word × 18Bit)Direct Rambus DRAM Module(I/O Frequency:600MHz）(64M字節(jié)(32M字× 18位)直接Rambus 動(dòng)態(tài)RAM模塊(I/O 頻率:600MHz）)
THMR1E4-7 33,554,432-Word（64MBytes) by 18-Bit(32M-Word × 18Bit)Direct Rambus DRAM Module(I/O Frequency:711MHz）(64M字節(jié)(32M字× 18位)直接Rambus 動(dòng)態(tài)RAM模塊(I/O 頻率:711MHz）)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
THMC51DBQR 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:
THMR1395 制造商:DELTA 制造商全稱(chēng):Delta Electronics, Inc. 功能描述:Through Hole Power Inductors
THMR1395-0R6 制造商:DELTA 制造商全稱(chēng):Delta Electronics, Inc. 功能描述:Through Hole Power Inductors
THMR1395-0R8 制造商:DELTA 制造商全稱(chēng):Delta Electronics, Inc. 功能描述:Through Hole Power Inductors
THMR1395-1R2 制造商:DELTA 制造商全稱(chēng):Delta Electronics, Inc. 功能描述:Through Hole Power Inductors
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*