參數(shù)資料
型號： THMC50SSOPDBQ
廠商： Texas Instruments, Inc.
英文描述： KPT 55C 55#20 SKT RECP
中文描述： 遠程/本地溫度監(jiān)視器和通風機的SMBus接口控制器
文件頁數(shù)： 7/32頁
文件大?。?/td> 437K
代理商： THMC50SSOPDBQ
THMC50
REMOTE/LOCAL TEMPERATURE MONITOR AND
FAN CONTROLLER WITH SMBus INTERFACE
SLIS090 – JULY 1999
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
ac electrical characteristics, V
CC3
= V
(VCC3AUX)
= 3.3 V, T
A
= 25
°
C (see Notes 6 and 7) (unless
otherwise noted)
temperature-to-digital converter timing parameters: Remote_Diode+, Remote_Diode–
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
t(SAMPLE)
Temperature-to-digital acquisition sample rate
0.75
1
1.25
sa/s
reset function timing parameters: VCC3, VCC3AUX, MR, AUXRST, RST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
t(RP)
t(VCC3RST)
t(VCC3AUX1)
t(VCC3AUX2)
t(MR)
t(RST)
t(MRMIN)
t(AUXRSTMIN)
t(GLITCH)
RST and AUXRST pulse duration
See Figures 17–20
140
560
ms
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
ns
VCC3 to RST delay
See Figures 17–20
20
VCC3AUX to AUXRST delay
See Figures 17–20
20
VCC3AUX to RST delay
See Figures 17–20
20
MR input to RST delay
See Figures 17–20
0.5
AUXRST input to RST delay
See Figures 17–20
0.5
MR input minimum pulse width
10
AUXRST input minimum pulse width
10
MR, AUXRST glitch immunity
100
SMBus interface timing parameters: SCL, SDA
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
f(SCL)
t(BUF)
SCL operating frequency
See Figure 1
10
100
kHz
μ
s
Bus free time between stop and start condition
See Figure 1
4.7
t(HDSTA)
Hold time after (repeated) start condition. After this period,
the first clock is generated
See Figure 1
4
μ
s
t(SUSTA)
t(SUSTO)
t(HDDAT)
t(SUDAT)
t(LOW)
t(HIGH)
t(LOWSEXT)
t(LOWMEXT)
tF
tR
NOTES:
Repeated start condition setup time
See Figure 1
4.7
μ
s
μ
s
ns
Stop condition setup time
See Figure 1
4
Data hold time
See Figure 1
300
Data setup time
See Figure 1
250
ns
μ
s
μ
s
ms
SCL clock low period
See Figure 1
4.7
SCL clock high period
See Figure 1
4
50
Cumulative clock low extend time (slave device)
See Figure 1
25
Cumulative clock low extend time (master device)
See Figure 1
10
ms
Clock/data fall time
See Figure 1
300
ns
Clock/data rise time
See Figure 1
1000
ns
6. Typicals are at TJ = TA = 25
°
C with V(VCC3AUX) = 3.3 V and represent most likely parametric norm.
7. Timing specifications are tested at the TTL logic levels, VIL = 0.4 V for a falling edge and VIH = 2.4 V for a rising edge. The 3-state
output voltage is forced to 1.4 V.
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