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參數(shù)資料
| 型號(hào)： | THS1041IPWRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | GREEN, PLASTIC, TSSOP-28 |
| 文件頁(yè)數(shù)： | 12/41頁(yè) |
| 文件大?。?/td> | 810K |
| 代理商： | THS1041IPWRG4 |
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THS1041
SLAS289C OCTOBER 2001 REVISED OCTOBER 2004
2
www.ti.com
AVAILABLE OPTIONS
PRODUCT
PACKAGE
LEAD
PACKAGE
DESGIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKINGS
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
THS1041C
0
°C to 70°C
TH1041
THS1041CPW
Tube, 50
THS1041C
TSSOP28
PW
0
°C to 70°C
TH1041
THS1041CPWR
Tube and Reel, 2000
THS1041I
TSSOP28
PW
40
°C to 85°C
TJ1041
THS1041IPW
Tube, 50
THS1041I
40
°C to 85°C
TJ1041
THS1041IPWR
Tube and Reel, 2000
THS1041C
0
°C to 70°C
TH1041
THS1041CDW
Tube, 20
THS1041C
SOP28
DW
0
°C to 70°C
TH1041
THS1041CDWR
Tube and Reel, 1000
THS1041I
SOP28
DW
40
°C to 85°C
TJ1041
THS1041IDW
Tube, 20
THS1041I
40
°C to 85°C
TJ1041
THS1041IDWR
Tube and Reel, 1000
For the most current specification and package information, refer to the TI web site at www.ti.com.
functional block diagram
10 Bit
DAC
SHPGA
10 Bit
ADC
Reference
Resistor
Digital
Interface
3-State
Output
Buffers
Mode
Detection
0.5 V
CLAMPOUT
CLAMP
AIN+
AIN
MODE
REFSENSE
VREF
REFB
REFT
WR
I/O (09)
OVR
OE
Timing
Circuit
CLK
AVDD
AGND
CLAMPIN
Clamp
Logic
Clamp
Logic
Clamp
Logic
A2
+
A1
VREF
DVDD
DGND
NOTE: A1 Internal bandgap reference
A2 Internal ADC reference generator
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| THS1041CDWG4 | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| THS1041IDW | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| THS1041IDWG4 | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| THS1041IPWR | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| THS1041IPWG4 | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
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參數(shù)描述 |
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