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參數(shù)資料
| 型號： | THS1060CPHP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT DELTA-SIGMA ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | POWER, PLASTIC, TQFP-48 |
| 文件頁數(shù)： | 8/21頁 |
| 文件大?。?/td> | 356K |
| 代理商： | THS1060CPHP |
THS1060
10-BIT 60 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS212A – MARCH 2000 – REVISED MARCH 2001
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
CLK+
VCM
THS1060
CLK–
Impedance Ratio = 1:4
3 V – 5 V p-p
0.01
F
0.1
F
T4-1H
Zo
4 Zo
0.1
F
Figure 21. Coaxial Clock Source
The clock signals, CLK+ and CLK– should be well matched and must both be driven.
A transformer ensures minimal skew between the two complementary channels. However, skew levels of up
to 500 ps between CLK+ and CLK– can be tolerated with some performance degradation.
The clock input can also be driven differentially with a 5-V TTL signal by using an RF transformer to convert the
TTL signal to a differential signal. The TTL signal is ac coupled to the positive primary terminal with a high pass
circuit. The negative terminal of the transformer is connected to ground (see Figure 22). The transformer
secondary is connected to the CLK inputs.
CLK+
CLK–
VCM
THS1060
0.01
F
0.1
F
5 V TTL CLK
0.1
F
Impedance Ratio = 1:4
T4 - 1H
Figure 22. TTL Clock Input
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| THS1060I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT 60 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER |
| THS1060IPHP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| THS1060PHP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT 60 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER |
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