參數(shù)資料
型號: THS1206MDAREP
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 4-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
封裝: GREEN, PLASTIC, TSSOP-32
文件頁數(shù): 18/43頁
文件大?。?/td> 799K
代理商: THS1206MDAREP
THS1206EP
12BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOGTODIGITAL CONVERTERS
SGLS126A JULY 2002 REVISED FEBRUARY 2003
25
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing and signal description of the THS1206 (continued)
read timing (using RD, RD-controlled)
Figure 15 shows the read-timing behavior when the WR(R/W) input is programmed as a write-input only. The
input RD acts as the read-input in this configuration. This timing is called RD-controlled because RD is the last
external signal of CS0, CS1, and RD which becomes valid.
90%
10%
tw(RD)
tsu(CS)
th(CS)
ta
th
td(CSDAV)
CS0
CS1
WR
RD
D(011)
DATA_AV
10%
Figure 15. Read Timing Diagram Using RD (RD-controlled)
read timing parameter (RD-controlled)
PARAMETER
MIN
TYP
MAX
UNIT
tsu(CS)
Setup time, RD low to last CS valid
0
ns
ta
Access time, last CS valid to data valid
0
10
ns
td(CSDAV) Delay time, last CS valid to DATA_AV inactive
12
ns
th
Hold time, first CS invalid to data invalid
0
5
ns
th(CS)
Hold time, RD change to first CS invalid
5
ns
tw(RD)
Pulse duration, RD active
10
ns
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