參數(shù)資料
型號： THS1207IDAG4
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 4-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
封裝： GREEN, PLASTIC, TSSOP-32
文件頁數(shù)： 16/32頁
文件大?。?/td> 317K
代理商： THS1207IDAG4
THS1207
SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002
www.ti.com
23
Read Timing (using RD, RD-controlled)
Figure 32 shows the read-timing behavior when the WR(R/W) input is programmed as a write-input only. The input
RD acts as the read-input in this configuration. This timing is called RD-controlled because RD is the last external
signal of CS0, CS1, and RD which becomes valid.
90%
10%
tw(RD)
tsu(CS)
th(CS)
ta
th
td(CSDAV)
CS0
CS1
WR
RD
D(0–9)
DATA_AV
10%
Figure 32. Read Timing Diagram Using RD (RD-controlled)
Read Timing Parameter (RD-controlled)
PARAMETER
MIN
TYP
MAX
UNIT
tsu(CS)
Setup time, RD low to last CS valid
0
ns
ta
Access time, last CS valid to data valid
0
10
ns
td(CSDAV) Delay time, last CS valid to DATA_AV inactive
12
ns
th
Hold time, first CS invalid to data invalid
0
5
ns
th(CS)
Hold time, RD change to first CS invalid
5
ns
tw(RD)
Pulse duration, RD active
10
ns
相關(guān)PDF資料
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THS1207CDAG4 4-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
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