參數(shù)資料
型號(hào)： THS1207IDAG4
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 4-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
封裝： GREEN, PLASTIC, TSSOP-32
文件頁數(shù)： 8/32頁
文件大小： 317K
代理商： THS1207IDAG4
THS1207
SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002
www.ti.com
16
Figure 28 shows the conversion timing when 3 analog input channels are selected. The maximum throughput
rate per channel is 2 MSPS in this mode. The data flow in the bottom of the figure shows in which order the
converted data is available to the databus. The signal SYNC is always active low if data of channel one is
available to the databus. The data of channel one is followed by the data of channel two and data of channel
three before channel one is again available to the data bus and SYNC is active low.
Sample N
Channel 1, 2, 3
Sample N+1
Channel 1, 2, 3
Sample N+2
Channel 1, 2, 3
Data N–1
Channel 3
Data N
Channel 1
Data N
Channel 2
Data N
Channel 3
Data N–2
Channel 3
Data N–1
Channel 1
Data N–1
Channel 2
AIN
CONV_CLK
READ
READ is the logical combination from CS0, CS1 and RD
SYNC
td(A)
td(pipe)
tw(CONV_CLKH)
tw(CONV_CLKL)
tc
tsu(CONV_CLKL-READL)
tsu(READH-CONV_CLKL)
td(CONV_CLKL-SYNCL)
td(CONV_CLKL-SYNCH)
Figure 28. Conversion Timing in 3-Channel Operation
Figure 29 shows the timing of the conversion mode where 4 analog input channels are selected. The maximum
throughput rate per channel is 1.5 MSPS in this mode. The data flow in the bottom of the figure shows in which
order the converted data is available to the databus. The signal SYNC is active low when data of channel one
is available to the databus. The data of channel one is followed by the data of channel two, data of channel three
and data of channel 4 before channel one is again available to the data bus and SYNC is active low.
Sample N
Channel 1, 2, 3, 4
Sample N+1
Channel 1, 2, 3, 4
Data N–1
Channel 4
Data N
Channel 1
Data N
Channel 2
Data N
Channel 3
Data N–1
Channel 1
Data N–1
Channel 2
Data N–1
Channel 3
AIN
CONV_CLK
READ
READ is the logical combination from CS0, CS1 and RD
SYNC
td(A)
td(pipe)
tw(CONV_CLKH)
tw(CONV_CLKL)
tc
tsu(CONV_CLKL-READL)
tsu(READH-CONV_CLKL)
tsu(CONV_CLKL-SYNCH)
tsu(CONV_CLKL-SYNCL)
Figure 29. Timing of Continuous Conversion Mode (4-channel operation)
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THS1207CDAG4 4-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
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