參數(shù)資料
型號： THS1209CDA
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 2-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
封裝： GREEN, PLASTIC, TSSOP-32
文件頁數(shù)： 18/33頁
文件大小： 312K
代理商： THS1209CDA
THS1209
SLAS288B – JULY 2000 – REVISED DECEMBER 2002
www.ti.com
25
Write Timing (using WR, WR-controlled)
Figure 30 shows the write-timing behavior when the WR(R/W) input is programmed as a write input WR only. The
input RD acts as the read input in this configuration. This timing is called WR-controlled because WR is the last
external signal of CS0, CS1, and WR which becomes valid.
90%
10%
tsu
th
D(0–9)
DATA_AV
10%
tw(WR)
tsu(CS)
th(CS)
CS0
CS1
WR
RD
Figure 30. Write Timing Diagram Using WR (WR-controlled)
Write Timing Parameter Using WR (WR-controlled)
PARAMETER
MIN
TYP
MAX
UNIT
tsu(CS)
Setup time, CS stable to last WR valid
0
ns
tsu
Setup time, data valid to first WR invalid
5
ns
th
Hold time, WR invalid to data invalid
2
ns
th(CS)
Hold time, WR invalid to CS change
5
ns
tw(WR)
Pulse duration, WR active
10
ns
相關PDF資料
PDF描述
THS1209CDAG4 2-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
THS1209IDAG4 2-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
THS1215CDWRG4 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
THS1215IDWRG4 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
THS1215CPWRG4 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
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