參數(shù)資料
型號(hào)： THS1209CDA
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： ADC
英文描述： 2-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
封裝： GREEN, PLASTIC, TSSOP-32
文件頁(yè)數(shù)： 28/33頁(yè)
文件大小： 312K
代理商： THS1209CDA
THS1209
SLAS288B – JULY 2000 – REVISED DECEMBER 2002
www.ti.com
4
ELECTRICAL CHARACTERISTICS
over recommended operating conditions, VREF = internal, fs = 8 MSPS, fI = 2 MHz at –1 dBFS (unless otherwise noted)
AC SPECIFICATIONS, AVDD = DVDD = 5 V, BVDD = 3.3 V, CL < 30 pF
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SINAD
Signal to noise ratio + distortion
Differential mode
63
65
dB
SINAD
Signal-to-noise ratio + distortion
Single-ended mode
62
64
dB
SNR
Signal to noise ratio
Differential mode
64
69
dB
SNR
Signal-to-noise ratio
Single-ended mode
64
68
dB
THD
Total harmonic distortion
Differential mode
–70
–67
dB
THD
Total harmonic distortion
Single-ended mode
–68
–64
dB
ENOB
Effective number of bits
Differential mode
10.17
10.5
Bits
ENOB
(SNR)
Effective number of bits
Single-ended mode
10
10.3
Bits
SFDR
Spurious free dynamic range
Differential mode
67
71
dB
SFDR
Spurious free dynamic range
Single-ended mode
65
69
dB
Analog Input
Full-power bandwidth with a source impedance of 150
in
differential configuration.
Full scale sinewave, –3 dB
98
MHz
Full-power bandwidth with a source impedance of 150
in
single-ended configuration.
Full scale sinewave, –3 dB
54
MHz
Small-signal bandwidth with a source impedance of 150
in
differential configuration.
100 mVpp sinewave, –3 dB
98
MHz
Small-signal bandwidth with a source impedance of 150
in
single-ended configuration.
100 mVpp sinewave, –3 dB
54
MHz
TIMING REQUIREMENTS
AVDD = DVDD = 5 V, BVDD = 3.3 V, VREF = internal, CL < 30 pF
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tpipe
Latency
5
CONV
CLK
tsu(CONV_CLKL-READL)
Setup time, CONV_CLK low before CS valid
10
ns
tsu(READH-CONV_CLKL)
Setup time, CS invalid to CONV_CLK low
20
ns
td(CONV_CLKL-SYNCL)
Delay time, CONV_CLK low to SYNC low
10
ns
td(CONV_CLKL-SYNCH)
Delay time, CONV_CLK low to SYNC high
10
ns
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