參數(shù)資料
型號: THS1240I
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 1-CH 12-BIT DELTA-SIGMA ADC, PARALLEL ACCESS, PQFP48
封裝: POWER, PLASTIC, TQFP-48
文件頁數(shù): 19/19頁
文件大?。?/td> 424K
代理商: THS1240I
THS1240
12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS279A – JUNE 2000 – REVISED AUGUST 2000
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
using the THS1240 clock input (continued)
If the dc component of the input clock differs from VDD/2 by more than 10%, it is best to connect the CLK+ input
to the clock source through a 0.01
F capacitor. In this mode, the converter can operate with a clock having a
peak-to-peak voltage of as little as 2 V with little or no performance degradation (see Figure 9).
CLK+
THS1240
CLK–
Square Wave or
Sine Wave
2 V p-p to 5 V p-p
0.01
F
0.01
F
Figure 9. AC Coupled Single-Ended Clock Input
The THS1240 clock input can also be driven differentially. If the common mode of the clock input is VDD/2, then
the clock inputs can be driven directly (see Figure 10)
CLK+
THS1240
CLK–
Differential Square Wave or
Sine Wave 2 V p-p to 5 V p-p
Common Mode Voltage = VDD/2
Figure 10. Differential Clock Input
If the clock input is driven differentially with a clock signal having a common mode voltage that is different from
VDD/2, then it is best to connect both clock inputs to the differential input clock signal with 0.01 F capacitors
(see Figure 11). The differential input swing can vary between 2 V and 5 V with little or no performance
degradation.
CLK+
THS1240
CLK–
Differential Square Wave or
Sine Wave
2 V p-p to 5 V p-p
0.01
F
0.01
F
Figure 11. AC Coupled Differential Clock Input
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