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參數(shù)資料
| 型號： | THS1240I |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 12-BIT DELTA-SIGMA ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | POWER, PLASTIC, TQFP-48 |
| 文件頁數(shù)： | 3/19頁 |
| 文件大?。?/td> | 424K |
| 代理商： | THS1240I |
THS1240
12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS279A – JUNE 2000 – REVISED AUGUST 2000
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
digital outputs
The digital outputs are in 2s complement format and can drive either TTL, 3-V CMOS, or 5-V CMOS logic. The
digital output high voltage level is equal to DRVDD. Table 1 shows the value of the digital output bits for full scale
analog input voltage, midrange analog input voltage, and negative full scale input voltage. To reduce capacitive
loading, each digital output of the THS1240 should drive only one digital input. The CMOS output drivers are
capable of handling up to a 15 pF load. For better SNR performance, use 3.3 V for DRVDD. Resistors of 200
in series with the digital output can be used for optimizing SNR performance.
Table 1. Digital Outputs
ANALOG INPUT
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
VIN+
VIN–
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Vref+
Vref–
0
1
VCM
0
Vref–
Vref+
1
0
power supplies
Best performance is obtained when AVDD is kept separate from DVDD. Regulated or linear supplies, as opposed
to switched power supplies, must be used to minimize supply noise. It is also recommended to partition the
analog and digital components on the board in such a way that the analog supply plane does not overlap with
the digital supply plane in order to limit dielectric coupling between the different supplies.
package
The THS1240 is packaged in a small 48-pin quad flat-pack PowerPAD
package. The die of the THS1240 is
bonded directly to copper alloy plate which is exposed on the bottom of the package. Although, the PowerPAD
provides superior heat dissipation when soldered to a ground land, it is not necessary to solder the bottom of
the PowerPAD
to anything in order to achieve minimum performance levels indicated in this specification over
the full recommended operating temperature range.
Only if the device is to be used at ambient temperatures above the recommended operating temperatures, use
of the PowerPAD
is suggested.
The copper alloy plate or PowerPAD
is exposed on the bottom of the device package for a direct solder
attachment to a PCB land or conductive pad. The land dimensions should have minimum dimensions equal to
the package dimensions minus 2 mm, see Figure 14.
For a multilayer circuit board, a second land having dimensions equal to or greater than the land to which the
device is soldered should be placed on the back of the circuit board (see Figure 15). A total of 9 thermal vias
or plated through-holes should be used to connect the two lands to a ground plane (buried or otherwise) having
a minimum total area of 3 inches square in 1 oz. copper. For the THS1240 package, the thermal via centers
should be spaced at a minimum of 1 mm. The ground plane need not be directly under or centered around the
device footprint if a wide ground plane thermal run having a width on the order of the device is used to channel
the heat from the vias to the larger portion of the ground plane. The THS1240 package has a standoff of 0.19
mm or 7.5 mils. In order to apply the proper amount of solder paste to the land, a solder paste stencil with a 6
mils thickness is recommended for this device. Too thin a stencil may lead to an inadequate connection to the
land. Too thick a stencil may lead to beading of solder in the vicinity of the pins which may lead to shorts. For
more information, refer to Texas Instruments literature number SLMA002
PowerPAD
Thermally Enhanced
Package.
PowerPAD is a trademark of Texas Instruments.
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