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參數(shù)資料
| 型號： | THS14F03EVM |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | THS14F03EVM(THS14F03評估板) |
| 中文描述： | THS14F03EVM（THS14F03評估板） |
| 文件頁數(shù)： | 23/39頁 |
| 文件大小： | 523K |
| 代理商： | THS14F03EVM |
Circuit Function
3-6
3.1.5
Interrupts
The ADC produces two signals that can be used to interrupt a DSP:
INT: This is routed via buffer U3 to the IN_EXT_INT pin on the daughter-
card connector.
FOVL: This is routed via buffer U3 to both BIDIR_ED14 and IN_TINP. This
gives the DSP code developer flexibility on using the signal in their system.
Note:
This function is only supported on the THS14F01 and THS14F03. Refer to
the device datasheet.
3.1.6
Hardware Loopback
The EVM can be configured by insertion of jumper links H12 and H13 to go into
a hardware loopback mode. This is primarily intended so that the board can
be put into an operational state when it is powered up stand-alone. The control
logic for this is explained in section 3.1.8.
3.1.7
ADC Write/Read Cycle
The following daughtercard address and control lines are mapped directly to
the ADC when performing a write to or a read from the device:
OUT_EA2 is mapped to A0
OUT_EA3 is mapped to A1
OUT_AWE is mapped to WRB
OUT_ARE is mapped to OEB
These, combined with the address decode logic described in section 3.1.8, al-
low direct control of the ADC operation via the normal write/read cycles of a
DSP.
3.1.8
Address Decode Logic
The EVM uses a Xilinx XC9536 (U9) CPLD to perform address decode and
control. The CPLD decodes the daughtercard address and strobe lines to con-
trol the ADC chip select and the buffer direction and output-enable states. The
Abel code used to generate the logic is given in Listing 3–1
.
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