參數(shù)資料
型號(hào): THS5641AIPWG4
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: PARALLEL, 8 BITS INPUT LOADING, 0.035 us SETTLING TIME, 8-BIT DAC, PDSO28
封裝: GREEN, PLASTIC, TSSOP-28
文件頁數(shù): 10/31頁
文件大小: 915K
代理商: THS5641AIPWG4
THS5641A
8BIT, 100 MSPS, CommsDAC
DIGITALTOANALOG CONVERTER
SLAS277A MARCH 2000 REVISED SEPTEMBER 2002
18
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
IOUT2
IOUT1
IOUT2
IOUT1
VOUT
100
+
RFB
+)
)
VOUT
+)
)
50
(a)
(b)
50
CFB
THS4001
THS4011
Figure 27. Differential and Single-Ended Output Configuration
The THS5641A can be easily configured to drive a doubly terminated 50
cable. Figure 28(a) shows the
single-ended output configuration, where the output current IOUT1 flows into an equivalent load resistance of
25
. Node IOUT2 should be connected to ground or terminated with a resistor of 25 . Differential-to-single
conversion (e.g., for measurement purposes) can be performed using a properly selected RF transformer, as
shown in Figure 28(b). This configuration provides maximum rejection of common-mode noise sources and
even order distortion components, thereby doubling the power to the output. The center tap on the primary side
of the transformer is connected to AGND, enabling a dc current flow for both IOUT1 and IOUT2. Note that the
ac performance of the THS5641A is optimum using this differential transformer coupled output, limiting the
voltage swing at IOUT1 and IOUT2 to
±0.5 V.
IOUT2
IOUT1
VOUT
IOUT2
IOUT1
VOUT
50
100
(a)
(b)
25
50
50
50
50
1:1
Figure 28. Driving a Doubly Terminated 50
Cable
相關(guān)PDF資料
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THS5641AIPWR PARALLEL, 8 BITS INPUT LOADING, 0.035 us SETTLING TIME, 8-BIT DAC, PDSO28
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THS5641AIDWG4 PARALLEL, 8 BITS INPUT LOADING, 0.035 us SETTLING TIME, 8-BIT DAC, PDSO28
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