參數(shù)資料
型號(hào): THS5641AIPWG4
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: PARALLEL, 8 BITS INPUT LOADING, 0.035 us SETTLING TIME, 8-BIT DAC, PDSO28
封裝: GREEN, PLASTIC, TSSOP-28
文件頁(yè)數(shù): 7/31頁(yè)
文件大小: 915K
代理商: THS5641AIPWG4
THS5641A
8BIT, 100 MSPS, CommsDAC
DIGITALTOANALOG CONVERTER
SLAS277A MARCH 2000 REVISED SEPTEMBER 2002
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
DAC transfer function
The THS5641A delivers complementary output currents IOUT1 and IOUT2. Output current IOUT1 equals the
approximate full-scale output current when all input bits are set high in mode 0 (straight binary input), i.e. the
binary input word has the decimal representation 255. For mode 1, the MSB is inverted (twos complement input
format). Full-scale output current will flow through terminal IOUT2 when all input bits are set low (mode 0,
straight binary input). The relation between IOUT1 and IOUT2 can thus be expressed as:
IOUT1
+ IOUT
FS * IOUT2
where IOUTFS is the full-scale output current. The output currents can be expressed as:
IOUT1
+ IOUT
FS
CODE
256
IOUT2
+ IOUT
FS
(255
* CODE)
256
where CODE is the decimal representation of the DAC data input word. Output currents IOUT1 and IOUT2 drive
resistor loads RLOAD or a transformer with equivalent input load resistance RLOAD. This would translate into
single-ended voltages VOUT1 and VOUT2 at terminal IOUT1 and IOUT2, respectively, of:
VOUT1
+ IOUT1
R
LOAD +
CODE
256
IOUT
FS
R
LOAD
VOUT2
+ IOUT2
R
LOAD +
(255–CODE)
256
IOUT
FS
R
LOAD
The differential output voltage VOUTDIFF can thus be expressed as:
VOUT
DIFF + VOUT1–VOUT2 +
(2CODE–255)
256
IOUT
FS
R
LOAD
The latter equation shows that applying the differential output will result in doubling of the signal power delivered
to the load. Since the output currents of IOUT1 and IOUT2 are complementary, they become additive when
processed differentially. Care should be taken not to exceed the compliance voltages at node IOUT1 and
IOUT2, which would lead to increased signal distortion.
相關(guān)PDF資料
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