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參數(shù)資料
| 型號： | THS6182DR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | LOW-POWER DISSIPATION ADSL LINE DRIVER |
| 中文描述： | 低功耗ADSL線路驅(qū)動器 |
| 文件頁數(shù)： | 5/35頁 |
| 文件大?。?/td> | 1242K |
| 代理商： | THS6182DR |
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THS6182
SLLS544G–SEPTEMBER 2002–REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating free-air temperature range, T
A
= 25°C, V
CC
= ±12 V, R
F
= 2 k
,
Gain = +5, I
ADJ
= Bias1 = Bias2 = 0 V, R
L
= 50
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC PERFORMANCE
T
A
= 25°C
T
A
= full range
T
A
= 25°C
T
A
= full range
T
A
= full range
T
A
= 25°C
T
A
= full range
T
A
= 25°C
T
A
= full range
1
20
Input offset voltage
25
mV
V
OS
V
CC
= ±5 V, ±12 V, ±15 V
0.5
10
Differential offset voltage
15
Offset drift
50
μV/°C
8
15
-Input bias current
20
I
IB
V
CC
= ±5 V, ±12 V, ±15 V
μA
8
15
+Input bias current
20
Z
OL
INPUT CHARACTERISTICS
Open loop transimpedance
R
L
= 1 k
, V
CC
= ±12 V, ±15 V
900
k
T
A
= 25°C
T
A
= full range
T
A
= 25°C
T
A
= full range
T
A
= 25°C
T
A
= full range
T
A
= 25°C
T
A
= full range
±2.7
±3.0
V
CC
= ±5 V
V
±2.6
±9.5
±9.8
V
ICR
Input common-mode voltage range
V
CC
= ±12 V
V
±9.3
±12.4
±12.7
V
CC
= ±15 V
V
±12.1
48
54
CMRR
Common-mode rejection ratio
V
CC
= ±5 V, ±12 V, ±15 V
dB
44
+Input
800
k
pF
R
I
Input resistance
-Input
30
C
i
LOGIC CONTROL CHARACTERISTICS
Input capacitance
1.7
V
IH
V
IL
I
IH
I
IL
Bias pin voltage for logic 1
2.0
Relative to GND pin voltage
V
Bias pin voltage for logic 0
0.8
Bias pin current for logic 1
V
IH
= 3.3 V, GND = 0 V
V
IL
= 0.5 V, GND = 0 V
4
30
μA
Bias pin current for logic 0
1
10
μA
Transition time, logic 0 to logic 1
(4)
1
μs
Transition time, logic 1 to logic 0
(4)
1
μs
(4)
Transition time is defined as the time from when the logic signal is applied to the time when the supply current has reached half its final
value.
LOGIC TABLE
(1)(2)
BIAS-1
0
1
0
1
BIAS-2
0
0
1
1
FUNCTION
Full bias mode
Mid bias mode
Low bias mode
Shutdown mode
DESCRIPTION
Amplifiers ON with lowest distortion possible (default state)
Amplifiers ON with power savings with a reduction in distortion performance
Amplifiers ON with enhanced power savings and a reduction of distortion performance
Amplifiers OFF and output has high impedance
(1)
(2)
The default state for all logic pins is a logic zero (0).
The GND pin useable range is from V
CC-
to (V
CC+
- 4 V).
5
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