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參數(shù)資料
| 型號(hào)： | THS8135PHP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 0.015 us SETTLING TIME, 10-BIT DAC, PQFP48 |
| 封裝： | GREEN, PLASTIC, HTQFP-48 |
| 文件頁數(shù)： | 20/25頁 |
| 文件大小： | 522K |
| 代理商： | THS8135PHP |
THS8135
TRIPLE 10BIT, 240 MSPS VIDEO DAC WITH TRILEVEL SYNC AND VIDEO
(ITUR.BT601)COMPLIANT FULL SCALE RANGE
SLAS343A MAY 2001 REVISED JUNE 2002
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
ABPb
45
O
Analog blue or Pb current output, capable of directly driving a double terminated 75-
coaxial cable
AGY
41
O
Analog green or Y current output, capable of directly driving a double terminated 75-
coaxial cable
ARPr
43
O
Analog red or Pr current output, capable of directly driving a double terminated 75-
coaxial cable
AVDD
40, 44
I
Analog power supply (3.3 V). All AVDD pins must be connected.
AVSS
42, 46
I
Analog ground
BCb0BCb9
101
I
Blue or Cb pixel data input. Signals with index 0 denote the least significant bits.
BLANK
23
I
Blanking control input, active low. A rising edge on CLK latches BLANK. When asserted, the ARPr, AGY, and
ABPb outputs are driven to the blanking level, irrespective of the value on the data inputs. SYNC takes
precedence over BLANK, so asserting SYNC (low) while BLANK is active (low) results in sync generation.
The amplitude of the DAC outputs during BLANK active are determined by the color space and input code
range configurations of the device. BLANK control is available in both video and generic DAC modes.
CLK
26
I
Clock input. A rising edge on CLK latches RCr09, GY09, BCb09, BLANK, SYNC, and SYNC_T.
In video DAC mode, the M1 and M2 inputs are latched by a rising edge on CLK as well but only when additional
conditions are satisfied as explained in their terminal description.
In generic DAC mode, M1 and M2 are continuously interpreted i.e. independent of additional conditions, to
determine color space and input data formats. This allows easier configuration.
COMP
39
O
Compensation terminal. A 0.1-
F capacitor must be connected between COMP and AVDD.
DVDD
12
I
Digital power supply (1.8 V)
DVSS
11
I
Digital ground
FSADJ
38
I
Full-scale adjust control. The full-scale current drive on each of the output channels is determined by the value
of a resistor RFS connected between this terminal and AVSS. Figure 5 shows the relationship between
full-scale output voltage compliance and RFS for the nominal DAC termination of 37.5 .
GY0GY9
3627
I
Green or Y pixel data input. Signals with index 0 denote the least significant bits.
M1
47
I
Operation mode control 1.
In video DAC mode, the second rising edge on CLK after a transition on SYNC latches M1. The interpretation
is dependent on the polarity of the last SYNC transition:
SYNC L
→ H: latched as M1_INT
SYNC H
→ L: latched as BLNK_INT.
Together with M2_INT, M1_INT configures the device as shown in Table 2 for video DAC mode. BLNK_INT
determines if the device operates with the full- or reduced-scale input code range. Together with the color
space configuration, this sets the amplitude of the blanking level on the analog output(s) as shown in Table 5.
In generic DAC mode, M1 is continuously interpreted as M1_INT, BLNK_INT control is not available and the
device always assumes full-scale input code range for blank level positioning.
M2
48
I
Operation mode control 2.
In video DAC mode, the second rising edge on CLK after a transition on SYNC latches M2. The interpretation
is dependent on the polarity of the last SYNC transition:
SYNC L
→ H: latched as M2_INT
SYNC H
→ L: latched as INS3_INT
Together with M1_INT, M2_INT configures the device as shown in Table 3 for video DAC mode. When
INS3_INT is high, the device inserts sync on all DAC outputs; when low, sync is inserted only on the AGY
output.
In generic DAC mode, M2 is continuously interpreted as M2_INT, INS3_INT control is not applicable, since
sync insertion is not available in generic DAC mode.
RCr0RCr9
1322
I
Red or Cr pixel data input. Signals with index 0 denote the least significant bits.
SYNC
24
I
Sync control input, active low. A rising edge on CLK latches SYNC. When asserted, only the AGY output
(when INS3_INT=L, see terminal M2) for sync-on-G/Y, or ARPr, AGY, and ABPb outputs (when INS3_INT=H,
see terminal M2) for sync-on-all, are driven to the sync level, irrespective of the values on the data or BLANK
inputs. Therefore, SYNC should remain low for the whole duration of sync, which is in the case of a tri-level
sync both the negative and positive portion. See Figure 10 for timing control. SYNC control is only available in
video DAC mode.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| THS8135PHP | 制造商:Texas Instruments 功能描述:10BIT DAC 240MSPS TRIPLE SMD |
| THS8135PHPG4 | 功能描述:數(shù)字化視頻/模擬轉(zhuǎn)換器集成電路 Tr 10B 240MSPS Video DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:3 輸出類型:Current 轉(zhuǎn)換速率:180 MSPs 分辨率:10 bit 接口類型:Parallel 電壓參考:Internal or External 積分非線性:- 2.5 LSB, 1.5 LSB 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:HTQFP 封裝:Tray |
| THS8136 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:TRIPLE 10-BIT 180-MSPS GRAPHICS AND VIDEO DAC |
| THS8136IPHP | 功能描述:數(shù)字化視頻/模擬轉(zhuǎn)換器集成電路 Triple 10B 180MSPS Graphics & Video DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:3 輸出類型:Current 轉(zhuǎn)換速率:180 MSPs 分辨率:10 bit 接口類型:Parallel 電壓參考:Internal or External 積分非線性:- 2.5 LSB, 1.5 LSB 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:HTQFP 封裝:Tray |
| THS8136IPHPR | 功能描述:數(shù)字化視頻/模擬轉(zhuǎn)換器集成電路 Triple 10B 180MSPS Graphics & Video DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:3 輸出類型:Current 轉(zhuǎn)換速率:180 MSPs 分辨率:10 bit 接口類型:Parallel 電壓參考:Internal or External 積分非線性:- 2.5 LSB, 1.5 LSB 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:HTQFP 封裝:Tray |
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