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參數(shù)資料
| 型號(hào)： | THS8135PHP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 0.015 us SETTLING TIME, 10-BIT DAC, PQFP48 |
| 封裝： | GREEN, PLASTIC, HTQFP-48 |
| 文件頁數(shù)： | 24/25頁 |
| 文件大?。?/td> | 522K |
| 代理商： | THS8135PHP |
THS8135
TRIPLE 10BIT, 240 MSPS VIDEO DAC WITH TRILEVEL SYNC AND VIDEO
(ITUR.BT601)COMPLIANT FULL SCALE RANGE
SLAS343A MAY 2001 REVISED JUNE 2002
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Table 4. THS8135 RGB/YCbCr Color Space and Input Formatter Configuration
M1_INT
M2_INT
CONFIGURATION
DESRIPTION
L
GBR
3x10b4:4:4
GBR mode 4:4:4. Data clocked in on each rising edge of CLK from G, B, and R input channels.
L
H
YCbCr 3x10b4:4:4
YCbCr mode 4:4:4. Data clocked in on each rising edge of CLK from Y, Cb, and Cr input channels.
H
L
YCbCr 2x10b4:2:2
YCbCr mode 4:2:2 2x10 bit. Data clocked in on each rising edge of CLK from Y channel. A sample
sequence of Cb-Cr should be applied to the Cr port. At the first rising edge of CLK after BLANK is
taken high, Cb should be present on this port.
H
YCbCr 1x10b4:2:2
YCbCr mode 4:2:2 1x10 bit (ITU-R.BT-656 compliant). Data clocked in on each rising edge of CLK
from Y channel. A sample sequence of Cb-Y-Cr-Y should be applied to the Y port. At the first rising
edge of CLK after BLANK is taken high, Cb should be present on this port.
selection of full- or reduced-scale ITU-R.BT601 modes (available in video DAC mode only)
In video DAC mode, BLNK_INT sets the blanking level generated on the DAC outputs as shown in Table 5. This
allows imposing a blanking level on the analog outputs corresponding to either full-scale code range or a
reduced-scale code range compliant to ITU-R.BT601. The blanking level is correctly positioned for either RGB
or YCbCr configurations, determined from the M1/M2 setting.
For generic DAC mode, BLNK_INT control is not available and the device always generates an output level
during BLANK low assuming full-scale input code range.
Table 5. Full-Scale or ITU.BT601 Reduced-Scale Mode Selection and
Impact on Blanking Level Positioning
M1_INT
M2_INT
BLNK_INT
AVAILABLE IN
VIDEO DAC (V)
AND
GENERIC DAC
OPERATION MODE
CHANNEL OUTPUT LEVEL
DURING BLANK ACTIVE
CORRESPONDING TO DAC
INPUT CODE:
GENERIC DAC
(G) MODES?
AGY
ABPb
ARPr
L
V, G
GBR 3x10b 4:4:4, full scale range
0
L
H
V
GBR 3x10b 4:4:4, ITUR.BT601-compliant range
64
L
H
L
V, G
YCbCr 3x10b 4:4:4, full scale range
0
512
L
H
V
YCbCr 3x10b 4:4:4, ITUR.BT601-compliant range
64
512
H
L
V
YCbCr 2x10b 4:2:2, ITUR.BT601-compliant range
64
512
H
L
H
V, G
YCbCr 2x10b 4:2:2, full scale range
0
512
H
L
V
YCbCr 1x10b 4:2:2, ITUR.BT601-compliant range
64
512
H
V, G
YCbCr 1x10b 4:2:2, full scale range
0
512
In full-scale range, the DAC is driven with input codes 0-1023 to the desired video level, set by the resistor
connected to the FSADJ terminal (e.g., a full-scale video amplitude of 700 mV when terminated into 37.5
and
when using the nominal RFS value).
In reduced-scale ITU-R.BT601 range, it is the intention that full-scale video amplitude is reached when the
device is driven with digital inputs within the input code range shown in Table 6. Note that the code range is
unequal between RGBY on one hand and CbCr on the other hand. Figure 1 through Figure 4 illustrates the
difference between ITU-R.BT601 reduced-scale and full-scale code range operation. In reduced-range
configuration, the B/Cb and R/Cr components are digitally amplitude scaled internally. Note that there is no
scaling on the G/Y component. Therefore, to accommodate the 700-mV video compliance on all components,
the DAC full-scale output current needs to be increased between full-scale and reduced scale modes by a factor
of 1023/(940-64) by decreasing RFS in that proportion.
This implementation has the advantage of avoiding amplitude scaling on the most critical G/Y component, while
still providing the possibility for instantaneous overshoot/undershoot on the analog component video output
when illegal signals according to ITU-R.BT601, such as super-black or super-white, are applied to the device.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| THS8135PHP | 制造商:Texas Instruments 功能描述:10BIT DAC 240MSPS TRIPLE SMD |
| THS8135PHPG4 | 功能描述:數(shù)字化視頻/模擬轉(zhuǎn)換器集成電路 Tr 10B 240MSPS Video DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:3 輸出類型:Current 轉(zhuǎn)換速率:180 MSPs 分辨率:10 bit 接口類型:Parallel 電壓參考:Internal or External 積分非線性:- 2.5 LSB, 1.5 LSB 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:HTQFP 封裝:Tray |
| THS8136 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:TRIPLE 10-BIT 180-MSPS GRAPHICS AND VIDEO DAC |
| THS8136IPHP | 功能描述:數(shù)字化視頻/模擬轉(zhuǎn)換器集成電路 Triple 10B 180MSPS Graphics & Video DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:3 輸出類型:Current 轉(zhuǎn)換速率:180 MSPs 分辨率:10 bit 接口類型:Parallel 電壓參考:Internal or External 積分非線性:- 2.5 LSB, 1.5 LSB 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:HTQFP 封裝:Tray |
| THS8136IPHPR | 功能描述:數(shù)字化視頻/模擬轉(zhuǎn)換器集成電路 Triple 10B 180MSPS Graphics & Video DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:3 輸出類型:Current 轉(zhuǎn)換速率:180 MSPs 分辨率:10 bit 接口類型:Parallel 電壓參考:Internal or External 積分非線性:- 2.5 LSB, 1.5 LSB 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:HTQFP 封裝:Tray |
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