參數(shù)資料
型號(hào)： TLC1543QN
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 11-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP20
封裝： ROHS COMPLIANT, PLASTIC, DIP-20
文件頁數(shù)： 3/36頁
文件大小： 748K
代理商： TLC1543QN
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10BIT ANALOGTODIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052F MARCH 1992 REVISED JANUARY 2004
11
WWW.TI.COM
operating characteristics over recommended operating free-air temperature range,
VCC = Vref+ = 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz (unless otherwise noted) (continued)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPZH, tPZL
Enable time, CS
↓ to DATA OUT (MSB driven)
See Figure 3
1.3
s
tPHZ, tPLZ
Disable time, CS
↑ to DATA OUT (high impedance)
See Figure 3
150
ns
tr(EOC)
Rise time, EOC
See Figure 8
300
ns
tf(EOC)
Fall time, EOC
See Figure 7
300
ns
tr(DATA)
Rise time, data bus
See Figure 6
300
ns
tf(DATA)
Fall time, data bus
See Figure 6
300
ns
td(I/O-CS)
Delay time, tenth I/O CLOCK
↓ to CS↓ to abort conversion
(see Note 11)
9
s
All typical values are at TA = 25°C.
NOTE 11. Any transitions of CS are recognized as valid only if the level is maintained for a setup time plus two falling edges of the internal clock
(1.425
s) after the transition.
PARAMETER MEASUREMENT INFORMATION
EOC
CL = 50 pF
12 k
DATA OUT
Test Point
VCC
RL = 2.18 k
CL = 100 pF
12 k
Test Point
VCC
RL = 2.18 k
Figure 2. Load Circuits
CS
DATA
OUT
2.4 V
0.4 V
90%
10%
tPZH, tPZL
tPHZ, tPLZ
0.8 V
2 V
Figure 3. DATA OUT Enable and Disable
Voltage Waveforms
ADDRESS
th(A)
0.8 V
2 V
I/O CLOCK
Address
Valid
tsu(A)
0.8 V
Figure 4. ADDRESS Setup and Hold TIme
Voltage Waveforms
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