參數(shù)資料
型號： TLC1543QN
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 11-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP20
封裝： ROHS COMPLIANT, PLASTIC, DIP-20
文件頁數(shù)： 35/36頁
文件大?。?/td> 748K
代理商： TLC1543QN
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10BIT ANALOGTODIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052F MARCH 1992 REVISED JANUARY 2004
8
WWW.TI.COM
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC (see Note 1)
0.5 V to 6.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI
0.3 V to VCC + 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO
0.3 V to VCC + 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Positive reference voltage, Vref+
VCC + 0.1 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative reference voltage, Vref
0.1 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak input current (any input)
±20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak total input current (all inputs)
±30 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: TLC1542C, TLC1543C
0
°C to 70°C
. . . . . . . . . . . . . . . . . . . . . . .
TLC1542I, TLC1543I
40
°C to 85°C
. . . . . . . . . . . . . . . . . . . . . . . .
TLC1542Q, TLC1543Q
40
°C to 125°C
. . . . . . . . . . . . . . . . . . . . .
TLC1542M
55
°C to 125°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg
65
°C to 150°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds
260
°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to digital ground with REF and GND wired together (unless otherwise noted).
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage, VCC
4.5
5
5.5
V
Positive reference voltage, Vref + (see Note 2)
VCC
V
Negative reference voltage, Vref (see Note 2)
0
V
Differential reference voltage, Vref + Vref (see Note 2)
2.5
VCC VCC + 0.2
V
Analog input voltage (see Note 2)
0
VCC
V
High-level control input voltage, VIH
VCC = 4.5 V to 5.5 V
2
V
Low-level control input voltage, VIL
VCC = 4.5 V to 5.5 V
0.8
V
Setup time, address bits at data input before I/O CLOCK
↑, tsu(A) (see Figure 4)
100
ns
Hold time, address bits after I/O CLOCK
↑, th(A) (see Figure 4)
0
ns
Hold time, CS low after last I/O CLOCK
↓, th(CS) (see Figure 5)
0
ns
Setup time, CS low before clocking in first address bit, tsu(CS) (see Note 3 and Figure 5)
1.425
s
Clock frequency at I/O CLOCK (see Note 4)
0
2.1
MHz
Pulse duration, I/O CLOCK high, twH(I/O)
190
ns
Pulse duration, I/O CLOCK low, twL(I/O)
190
ns
Transition time, I/O CLOCK, tt(I/O) (see Note 5 and Figure 6)
1
s
Transition time, ADDRESS and CS, tt(CS)
10
s
TLC1542C, TLC1543C
0
70
Operating free-air temperature, TA
TLC1542I, TLC1543I
40
85
°C
Operating free-air temperature, TA
TLC1542Q, TLC1543Q
40
125
°C
TLC1542M
55
125
NOTES:
2. Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied
to REF convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref + Vref ); however,
the electrical specifications are no longer applicable.
3. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CS
↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the
minimum CS setup time has elapsed.
4. For 11- to 16-bit transfers, after the tenth I/O CLOCK falling edge (
≤ 2 V) at least 1 I/O CLOCK rising edge (≥ 2 V) must occur within
9.5
s.
5. This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of
normal room temperature, the devices function with input clock transition time as slow as 1
s for remote data-acquisition
applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
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