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參數(shù)資料
| 型號： | TLC2933PWLE |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | HIGH-PERFORMANCE PHASE-LOCKED LOOP |
| 中文描述： | 高性能鎖相環(huán) |
| 文件頁數(shù)： | 19/21頁 |
| 文件大?。?/td> | 367K |
| 代理商： | TLC2933PWLE |
TLC2933
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS136A – APRIL 1996 – REVISED JUNE 1997
19
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
Phase
Comparator
AGND
DGND
DGND
DGND
REF IN
DVDD
AVDD
VDD
LOGIC VDD (Digital)
LOGIC GND (Digital)
TEST
FIN–A
VCO INHIBIT
PFD INHIBIT
NC
VCO GND
VCO IN
BIAS
VCO VDD
VCO
R1
R3
C1
R2
C2
R5
R6
S1
S2
Divide
By
N
0.22
μ
F
1
2
3
4
5
6
7
14
13
12
11
10
9
8
FIN–B
RBIAS resistor
VCO OUT
PFD OUT
Figure 20. Evaluation and Operation Schematic
PCB layout considerations
The TLC2933 contains a high frequency oscillator; therefore, very careful breadboarding and PCB layout is
required for evaluation.
The following design recommendations benefit the TLC2933 user:
External analog and digital circuitry should be physically separated and shielded as much as possible to
reduce system noise.
Radio frequency (RF) breadboarding or RF PCB techniques should be used throughout the evaluation and
production process.
Wide ground leads or a ground plane should be used on the PCB layouts to minimize parasitic inductance
and resistance. The ground plane is the better choice for noise reduction.
LOGIC V
DD
and VCO V
DD
should be separate PCB traces and connected to the best filtered supply point
available in the system to minimize supply cross-coupling.
VCO V
DD
to ground and LOGIC V
DD
to ground should be decoupled with a 0.1-
μ
F capacitor placed as close
as possible to the appropriate device terminals.
The no-connection (NC) terminal on the package should be connected to ground to prevent stray pickup.
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