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參數(shù)資料
| 型號(hào)： | TLC2933PWLE |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | HIGH-PERFORMANCE PHASE-LOCKED LOOP |
| 中文描述： | 高性能鎖相環(huán) |
| 文件頁(yè)數(shù)： | 8/21頁(yè) |
| 文件大?。?/td> | 367K |
| 代理商： | TLC2933PWLE |
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TLC2933
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS136A – APRIL 1996 – REVISED JUNE 1997
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operating characteristics over recommended operating free-air temperature range, V
DD
= 5 V
(unless otherwise noted)
VCO section
PARAMETER
TEST CONDITIONS
RBIAS = 2.4 k
,, VCO IN = 1/2 VDD
Measured from VCO INHIBIT
↓
CL = 15 pF,
See Figure 3
CL = 15 pF,
See Figure 3
RBIAS = 2.4 k
, VCO IN = 1/2 VDD
RBIAS = 2.4 k
, VCO IN = 1/2 VDD,
TA = –20
°
C to 75
°
C
RBIAS = 2.4 k
, VCO IN = 2.5 V,
VDD = 4.75 V to 5.25 V
RBIAS = 2.4 k
MIN
TYP
MAX
UNIT
fosc
ts(fosc)
tr
tf
Operating oscillation frequency
64
80
96
MHz
μ
s
ns
Time to stable oscillation (see Note 8)
Rise time, VCO OUT
↑
Fall time, VCO OUT
↓
Duty cycle at VCO OUT
10
2.1
5
1.5
4
ns
45%
50%
55%
α
(fosc)
Temperature coefficient of oscillation frequency
0.03
%/
°
C
kSVS(fosc)
Supply voltage coefficient of oscillation frequency
0.02
%/mV
Jitter absolute (see Note 9)
100
ps
NOTES:
8: The time period to stabilize the VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.
9. Jitter performance is highly dependent on circuit layout and external device characteristics. The jitter specification was made with
a carefully designed printed circuit board (PCB) with no device socket.
PFD section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fmax
tPLZ
tPHZ
tPZL
tPZH
tr
tf
Maximum operating frequency
Disable time, PFD INHIBIT
↑
to PFD OUT Hi-Z
Disable time, PFD INHIBIT
↑
to PFD OUT Hi-Z
Enable time, PFD INHIBIT
↓
to PFD OUT low
Enable time, PFD INHIBIT
↓
to PFD OUT high
Rise time, PFD OUT
↑
Fall time, PFD OUT
↓
50
MHz
20
40
ns
See Figures 4 and 5 and Table 3
17
40
3.7
10
ns
3.4
10
CL= 15 pF See Figure 4
CL = 15 pF, See Figure 4
1.7
1.3
5
5
ns
ns
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