
TLC32044C, TLC32044E, TLC32044I, TLC32044M TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
27
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
serial port — AIC output signals
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tc(SCLK)
tf(SCLK)
tr(SCLK)
Shift clock (SCLK) cycle time
380
ns
Shift clock (SCLK) fall time
50
ns
Shift clock (SCLK) rise time
50
ns
Shift clock (SCLK) duty cycle
Delay from SCLK
↑
to FSR/FSX
↓
Delay from SCLK
↑
to FSR/FSX
↑
DR valid after SCLK
↑
Delay from SCLK
↑
to EODX/EODR
↓
in word mode
Delay from SCLK
↑
to EODX/EODR
↑
in word mode
EODX fall time
45
55
%
td(CH-FL)
td(CH-FH)
td(CH-DR)
td(CH-EL)
td(CH-EH)
tf(EODX)
tf(EODR)
td(CH-EL)
td(CH-EH)
td(MH-SL)
td(MH-SH)
CL = 50 pF
CL = 50 pF
52
ns
52
ns
90
ns
90
ns
90
ns
15
ns
EODR fall time
Delay from SCLK
↑
to EODX/EODR
↓
in byte mode
Delay from SCLK
↑
to EODX/EODR
↑
in byte mode
Delay from MSTR CLK
↑
to SCLK
↓
Delay from MSTR CLK
↑
to SCLK
↑
15
ns
100
ns
100
ns
65
ns
65
ns
serial port — AIC output signals, TLC32044M
MIN
TYP
MAX
UNIT
tc(SCLK)
tf(SCLK)
tr(SCLK)
Shift clock (SCLK) cycle time
400
ns
Shift clock (SCLK) fall time
50
ns
Shift clock (SCLK) rise time
50
ns
Shift clock (SCLK) duty cycle
Delay from SCLK
↑
to FSR/FSX
↓
Delay from SCLK
↑
to FSR/FSX
↑
DR valid after SCLK
↑
Delay from SCLK
↑
to EODX/EODR
↓
in word mode
Delay from SCLK
↑
to EODX/EODR
↑
in word mode
EODX fall time
50
%
td(CH-FL)
td(CH-FH)
td(CH-DR)
td(CH-EL)
td(CH-EH)
tf(EODX)
tf(EODR)
td(CH-EL)
td(CH-EH)
td(MH-SL)
td(MH-SH)
Typical values are at TA = 25
°
C.
260
ns
260
ns
316
ns
280
ns
280
ns
15
ns
EODR fall time
Delay from SCLK
↑
to EODX/EODR
↓
in byte mode
Delay from SCLK
↑
to EODX/EODR
↑
in byte mode
Delay from MSTR CLK
↑
to SCLK
↓
Delay from MSTR CLK
↑
to SCLK
↑
15
ns
100
ns
100
ns
65
ns
65
ns