參數(shù)資料
型號： TLC34076-85
廠商： Texas Instruments, Inc.
英文描述： Color-Palette(85MHz,與TLC34075兼容，另具24位和16位真彩色模式)
中文描述： 顏色調(diào)色板（85MHz，與TLC34075兼容，另具24位和16位真彩色模式）
文件頁數(shù)： 16/56頁
文件大?。?/td> 419K
代理商： TLC34076-85
FUNCTION
SCLK
BITS
2. . . 0
divide DOTCLK by
divide
DOTCLK
by
1
2
4
8
16
32
BITS
5. . .3
000
001
010
011
100
101
VCLK
2-4
Table 2–4. Output Clock Selection Register Format
BITS
3
0
1
0
1
0
1
X
X
X
X
X
X
X
X
5
0
0
0
0
1
1
1
X
X
X
X
X
X
X
4
0
0
1
1
0
0
1
X
X
X
X
X
X
X
2
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
X
X
X
X
X
X
X
0
0
1
1
0
0
1
0
X
X
X
X
X
X
X
0
1
0
1
0
1
X
VCLK frequency = DOTCLK frequency
VCLK frequency = DOTCLK frequency/2
VCLK frequency = DOTCLK frequency/4
VCLK frequency = DOTCLK frequency/8
VCLK frequency = DOTCLK frequency/16
VCLK frequency = DOTCLK frequency/32
VCLK output held at logic high level (default condition)§
SCLK frequency = DOTCLK frequency
SCLK frequency = DOTCLK frequency/2
SCLK frequency = DOTCLK frequency/4
SCLK frequency = DOTCLK frequency/8
SCLK frequency = DOTCLK frequency/16
SCLK frequency = DOTCLK frequency/32
SCLK output held at logic level low (default condition)§
Register bits 6 and 7 are don’t carebits.
When the clock selection is altered, a minimum 30-ns delay is incurred before the new clocks
are stabilized and running.
§These lines indicate the power-up conditions required to support the VGA pass-through mode.
Table 2–5. VCLK/SCLK Divide Ratio Selection
(Output Clock Selection Register Value in Hex)
000
001
010
011
100
101
1
2
4
8
16
32
00
08
10
18
20
28
01
09
11
19
21
29
02
0A
12
1A
22
2A
03
0B
13
1B
23
2B
04
0C
14
1C
24
2C
05
0D
15
1D
25
2D
Output clock selection register bits
2.3.1
SCLK
Data is latched inside the device on the rising edge of LOAD, which is basically the same as SCLK but not
disabled during BLANK active period. Therefore, SCLK must be set as a function of the pixel bus width and
the number of bit planes. SCLK can be selected as divisions of 1, 2, 4, 8, 16, or 32 of the dot clock. If SCLK
is not used, the output is switched off and held low to protect against VRAM lock-up due to invalid SCLK
frequencies. SCLK is also held low during the BLANK active period. The SCLK control timing has been
designed to interface directly with the external system VRAM. The shift register in the system VRAM should
be updated during the BLANK-active period. This allows the first SCLK out of BLANK to clock the VRAM
and enable the first group of pixel data to appear on the pixel bus, as well as at the TLC34076 pixel input
port. The second SCLK after BLANK latches the first group of pixel port data into the TLC34076 (see
Figure 2–2).
相關(guān)PDF資料
PDF描述
TLC34076-170 Color-Palette(170MHz,與TLC34075兼容，另具24位和16位真彩色模式)
TLC34076M-135 Color-Palette(135MHz,與TLC34075兼容，另具24位和16位真彩色模式)
TLC4501(中文) Self-Calibrating Dual Operational Amplifier(先進(jìn)LINEPIC，自校準(zhǔn)精密運(yùn)放)
TLC4502(中文) Self-Calibrating Operational Amplifier(先進(jìn)LINEPIC，雙組自校準(zhǔn)精密運(yùn)放)
TLC540(中文) 8-Bit Analog-To-Digital Converters With Serial Control And 11 Inputs(串行控制，75ksps,12通道，8位ADC)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TLC34076-85FN 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:
TLC34077 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette Data Manual
TLC34077135FN 制造商:TI 功能描述:*
TLC352 制造商:TI 制造商全稱:Texas Instruments 功能描述:LinCMOSE DUAL DIFFERENTIAL COMPARATOR
TLC352CD 功能描述:校驗器 IC Dual Differential RoHS:否 制造商:STMicroelectronics 產(chǎn)品: 比較器類型: 通道數(shù)量: 輸出類型:Push-Pull 電源電壓-最大:5.5 V 電源電壓-最小:1.1 V 補(bǔ)償電壓（最大值）:6 mV 電源電流（最大值）:1350 nA 響應(yīng)時間: 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SC-70-5 封裝:Reel
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*