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參數(shù)資料
| 型號： | TLC34076-85 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Color-Palette(85MHz,與TLC34075兼容，另具24位和16位真彩色模式) |
| 中文描述： | 顏色調(diào)色板（85MHz，與TLC34075兼容，另具24位和16位真彩色模式） |
| 文件頁數(shù)： | 21/56頁 |
| 文件大?。?/td> | 419K |
| 代理商： | TLC34076-85 |
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2-9
Mode 6c is a multiplexed version of mode 6a,, that allows two 16-bit TARGA-compatible words to be latched
into the TLC34076 pixel port with one SCLK. In this mode, the 16-bit word latched on pixel port inputs P0-P15
is executed first, while the word latched on P16-P31 is executed last. The user should program the SCLK
divide ratio in the output-clock selection register to /2. Refer to Table 2–8 for the exact bit definitions.
Mode 6d is a multiplexed version of mode 6b, that allows two 16-bit XGA-compatible words to be latched
into the TLC34076 pixel port with one SCLK. In this mode, the 16-bit word latched on pixel port inputs P0-P15
is executed first, while the word latched on P16-P31 is executed last. The user should program the SCLK
divide ratio in the output-clock selection register to /2. Refer to Table 2–8 for the exact bit definitions.
Mode 6e is a 24-bit true-color mode that features 8 bits of data for each color, as well as 8 bits of overlay
information. The order in which the color and overlay fields appear in the 32-bit word are the reverse of
mode 6f. Refer to Table 2–8 for the exact bit definitions.
Mode 6f is the 24-bit true-color mode used on the TLC34076. It also features 8 bits of data for each color,
as well as 8 bits of overlay information. Refer to Table 2–8 for the exact bit definitions.
Since only 5 bits (6 bits for GREEN in Mode 6b and 6d) are provided for each color in the 16-bit true-color
modes (6a–6d), the color data will be internally shifted by the TLC34076 to the 5 MSB positions (6 MSB
positions for GREEN in Mode 6b and 6d) before being presented to the three color DACs. The remaining
lower 3 bits (Iower 2 bits for GREEN in Modes 6b and 6d) are then set to logic 0.
When in true-color modes 6a or 6c, the internal palette-page register fills the remaining 7 MSB’s of overlay
data (see 1.2.3). This occurs because, in these modes, there is only one bit of overlay information presented
in the true-color word. In order to enable the true-color data to the DACs, all 8 overlay bits must be at logic
0. This can be accomplished by either writing zeros to the internal Palette Page Register and the overlay
bit, or by writing zeros to the internal Read Mask (see 2.4.6).
When in true-color modes 6e or 6f, the data input only works in the 8-bit mode. In other words, if only 6 bits
are to be used, the 2 LSB inputs for each color must be tied to GND. However, the palette, which is used
by the overlay input, is still governed by 8/6-input pin and the output MUX will select 8-bits data or 6-bits
data accordingly. The 8/6-input pin is also valid in the other 16-bit modes as well.
Both Little(default) and Big Endian data formats are supported by the true-color modes (see section 2.6.1
and Table 2–8 for more information).
2.4.5
The multiplexer is controlled via the 8-bit multiplex control register. The bit fields of the register are in
Table 2–6 and Table 2–7.
Multiplex Control Register
As an example of how to use Table 2–6, suppose that the design goals specify a system with eight data bits
per pixel and the lowest possible SCLK rate. Table 2–6 shows that, for non-VGA-pass-through operation,
only mode 4 supports an 8-bit pixel depth. The lowest-possible SCLK rate within mode 4 is 1:4. This set of
conditions is selected by writing the value 1Eh to the mux control register. The pixel latching sequence
column shows that, in this mode, P<7:0> should be connected to the earliest-displayed pixel plane, followed
by P<15:8>, P<23:16>, and then P<31:24> as the last displayed pixel plane. Assuming that VCLK is
programmed as DOTCLK/4, Table 2–5 shows that the 1:4 SCLK ratio is selected by writing the value 12h
to the output clock selection register. The special nibble mode should also be disabled (see Sections 2.9.2
and 2.11.2).
When the mux control register is loaded with 2Dh, the TLC34076 enters the VGA pass-through mode (the
same condition as the default power-up mode). Please refer to Section 2.5.4 for more details.
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相關(guān)代理商/技術(shù)參數(shù) |
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| TLC34076-85FN | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
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| TLC34077135FN | 制造商:TI 功能描述:* |
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| TLC352CD | 功能描述:校驗(yàn)器 IC Dual Differential RoHS:否 制造商:STMicroelectronics 產(chǎn)品: 比較器類型: 通道數(shù)量: 輸出類型:Push-Pull 電源電壓-最大:5.5 V 電源電壓-最小:1.1 V 補(bǔ)償電壓（最大值）:6 mV 電源電流（最大值）:1350 nA 響應(yīng)時間: 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SC-70-5 封裝:Reel |
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