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參數(shù)資料
| 型號： | TLC34076M-135 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Color-Palette(135MHz,與TLC34075兼容，另具24位和16位真彩色模式) |
| 中文描述： | 顏色調(diào)色板（135MHz，與TLC34075兼容，另具24位和16位真彩色模式） |
| 文件頁數(shù)： | 49/57頁 |
| 文件大?。?/td> | 456K |
| 代理商： | TLC34076M-135 |
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A–1
Appendix A
SCLK/VCLK and the TMS340x0
While the TLC34076M SCLK and VCLK outputs are designed for compatibility with all graphics systems,
they are also tightly coupled with the TMS340x0 graphics system processors. All the timing requirements
of the TMS340x0 have been considered. However, there are a few points that need to be explained with
regard to applications.
VCLK
All the video control signals in the TMS340x0 (i.e., BLANK, HSYNC, and VSYNC) are triggered and
generated from the falling edge of VCLK. The fact that the TLC34076M uses the falling edge to sample and
latch the BLANK input gives users maximum freedom to choose the frequency of VCLK and interconnect
the TLC34076M with the TMS340x0 GSP without glue logic. The VCLK frequency needs to be selected to
be compatible with the minimum VCLK period required by the TMS340x0.
In the TMS340x0, the same VCLK falling edge that generates BLANK requests a screen refresh. If the VCLK
period is longer than 16 TQs (TQ is the period of the TMS340x0 CLKIN), it is possible that the last SCLK
pulse could be used falsely to transfer the VRAM data from memory to the shift register along with the last
pixel transfer. The first SCLK pulse for the next scan line would then shift the first pixel data out of the pipe,
and the screen would then falsely start from the second pixel.
SCLK and SFLAG
The TLC34076M SCLK signal is compatible with current -10 and slower VRAMs. When split shift-register
transfers are used, one SCLK pulse has to be generated between the regular shift-register transfer and the
split shift-register transfer to ensure correct operation. The SFLAG input is designed for this purpose.
SFLAG can be generated from a programmable logic array and triggered by the rising edge of the TR/QE
signal or the rising edge of the RAS signal of the regular shift-register-transfer cycle. TR/QE can be used
if the minimum delay from when the VRAM TRG signal goes high to SCLK going high can be met by the
programmable logic array delay; otherwise, RAS can be used.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TLC34077 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette Data Manual |
| TLC34077135FN | 制造商:TI 功能描述:* |
| TLC352 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:LinCMOSE DUAL DIFFERENTIAL COMPARATOR |
| TLC352CD | 功能描述:校驗器 IC Dual Differential RoHS:否 制造商:STMicroelectronics 產(chǎn)品: 比較器類型: 通道數(shù)量: 輸出類型:Push-Pull 電源電壓-最大:5.5 V 電源電壓-最小:1.1 V 補償電壓（最大值）:6 mV 電源電流（最大值）:1350 nA 響應時間: 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:SC-70-5 封裝:Reel |
| TLC352CDG4 | 功能描述:校驗器 IC Dual Low Vltg LinCMOS Differential RoHS:否 制造商:STMicroelectronics 產(chǎn)品: 比較器類型: 通道數(shù)量: 輸出類型:Push-Pull 電源電壓-最大:5.5 V 電源電壓-最小:1.1 V 補償電壓（最大值）:6 mV 電源電流（最大值）:1350 nA 響應時間: 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:SC-70-5 封裝:Reel |
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