參數(shù)資料
型號(hào): TLC5617AIDR
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: SERIAL INPUT LOADING, 12.5 us SETTLING TIME, 10-BIT DAC, PDSO8
封裝: PLASTIC, SO-8
文件頁(yè)數(shù): 4/21頁(yè)
文件大?。?/td> 307K
代理商: TLC5617AIDR
TLC5617, TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS151B – JULY 1997 – REVISED MARCH 2000
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
buffer amplifier
The output buffer has a rail-to-rail output with short circuit protection and can drive a 2-k
load with a 100-pF
load capacitance. Settling time is a software selectable 12.5
s or 2.5 s typical to within ±0.5 LSB of the final
value.
external reference
The reference voltage input is buffered which makes the DAC input resistance not code dependent. Therefore,
the REFIN input resistance is 10 M
and the REFIN input capacitance is typically 5 pF, independent of input
code. The reference voltage determines the DAC full-scale output.
logic interface
The logic inputs function with CMOS logic levels. Most of the standard high-speed CMOS logic families may
be used.
serial clock and update rate
Figure 1 shows the TLC5617 timing. The maximum serial clock rate is
f
(SCLK)max +
1
t
w CH min )
t
w CL min
+ 20 MHz
The digital update rate is limited by the chip-select period, which is
tp(CS) + 16
t
w CH )
t
w CL
) t
su CS1
This equals 820-ns or 1.21-MHz update rate. However, the DAC settling time to 10 bits limits the update rate
for full-scale input step transitions.
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