參數(shù)資料
型號(hào)： TLE6711G
廠商： INFINEON TECHNOLOGIES AG
元件分類： 電源管理
英文描述： 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14
封裝： PLASTIC, SOP-14
文件頁(yè)數(shù)： 24/25頁(yè)
文件大小： 963K
代理商： TLE6711G
Data Sheet
8
Rev. 3.4, 2007-08-16
TLE 6711
Circuit Description
4
Circuit Description
Below some important sections of the TLE 6711 G/GL are described in more detail.
4.1
Power On Reset
In order to avoid any system failure, a sequence of several conditions has to be passed. In case of
V
CC power
down (
V
CC < VRT for t > tRR) a logic LOW signal is generated at the pin RO to reset an external microcontroller.
When the level of
V
CC reaches the reset threshold VRT, the signal at RO remains LOW for the Power-up reset delay
time
t
RD before switching to HIGH. If VCC drops below the reset threshold VRT for a time extending the reset
reaction time
t
RR, the reset circuit is activated and a power down sequence of period tRD is initiated. The reset
reaction time
t
RR avoids wrong triggering caused by short “glitches” on the VCC-line.
Figure 4
Reset Function
4.2
Watchdog Operation
The watchdog uses one hundred of the oscillator’s clock signal period as a timebase, defined as the watchdog
cycle time
t
CYL.
After power-on, the reset output signal at the RO pin (microcontroller reset) is kept LOW for the reset delay time
t
RD, i.e. 64 cycles. With the LOW to HIGH transition of the signal at RO the device starts the closed window time
t
CW = 32 cycles. A trigger signal within this window is interpreted as a pretrigger failure according to the figures
shown below. After the closed window the open window with the duration
t
OW is started. The open window lasts
at minimum until the trigger process has occurred, at maximum
t
OW is 32 cycles.
A HIGH to LOW transition of the watchdog trigger signal on pin WDI is taken by a trigger. To avoid wrong triggering
due to parasitic glitches two HIGH samples followed by two LOW samples (sample period
t
CYL) are decoded as a
valid trigger. If a trigger signal appears at the watchdog input pin WDI during the open window or a power up/down
occurs, the watchdog window signal is reset and a new closed window follows.
A reset is generated (RO goes LOW) if there is no trigger pulse during the open window or if a pretrigger occurs
during the closed window. This reset happens after 64 cycles after the latest valid closed window start time and
lasts for further 64 cycles.
The triggering is correct also, if the first three samples (two HIGH one LOW) of the trigger pulse at pin WDI are
inside the closed window and only the fourth sample (the second LOW sample) is taken in the open window.
In addition to the microcontroller reset signal RO the device generates a system enable signal at pin SEN. If RO
AET02950
L
H
RO
V
CC
Invalid
RT
V
typ. 4.65 V
< RR
t
< RD
t
Start-Up
ON Delay
Invalid
ON Delay
Started
Stopped
RD
t
RR
t
RD
t
Power
Start-Up
Normal
Failed
N
Failed
Normal
1 V
ON Delay
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TLE6711GXUMA1 制造商:Infineon Technologies AG 功能描述:DC/DC CONVERTER - Tape and Reel 制造商:Infineon Technologies AG 功能描述:IC REG BUCK BOOST ADJ PDSO14
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TLE6712GNTMA1 制造商:Infineon Technologies AG 功能描述:Firing Circuit 24-Pin DSO 制造商:Infineon Technologies AG 功能描述:AIRBAG_RESTRAINT_IC - Tape and Reel
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