參數(shù)資料
型號： TLE8242-2
廠商： INFINEON TECHNOLOGIES AG
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP64
封裝： GREEN, PLASTIC, LQFP-144
文件頁數(shù)： 11/78頁
文件大?。?/td> 1589K
代理商： TLE8242-2
Data Sheet
19
Rev. 1.0, 2010-02-09
TLE8242-2
Functional Description and Electrical Characteristics
Figure 8
Phase Synchronization Diagram
The TEST, SCI3, SCO2, SCO3, and AMUX pins are used during IC level test. These pins should be connected
directly to ground for normal device operation.
The FAULT pin is an open drain output pin. This pin will be pulled low by the device when an unmasked fault has
been detected. The fault masks are programmed via SPI message #1.
Electrical Characteristics:
V5D = 4.75V to 5.25V, Vbat = 5.5V to 42V,
T
j = -40 °C to +150 °C, all voltages with respect to ground, positive
current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
5.2.1
Logic input low voltage
V
ILMAX
––
0.8
V
5.2.2
Logic input high voltage
V
IHMIN
2.0
–
V
5.2.3
Logic output low voltage
V
OLMAX
––
0.2
V
I
L=200A
5.2.4
Logic output high voltage
V
OHMIN
0.8*V_
SIGNAL
––
V
I
L=-200A
5.2.5
Pull down digital input (SI, CLK,
SCK, PHASE_SYNC, ENABLE)
I
pd
10
–
50
A
V
in=V_SIGNAL
5.2.6
Pull up digital input (CS_B,
RESET_B)
I
pu
-50
–
-10
A
V
in=0V (Current
drain from
V_SIGNAL)
5.2.7
Fault pin voltage
V
fault.low
–
0.4
V
Active state;
I
fault=2mA
5.2.8
Fault pin current
I
fault,max
2.0
–
mA
Active state;
V
fault=0.4V
5.2.9
CLK high time (rise 2.0V to fall
2.0V)
t
14
8–
–ns
5.2.10
CLK low time (fall 0.8V to rise 0.8V)
t
15
8–
–ns
OUTx
PWM/32 CLK
PHASE_SYNC
T1
gate turns off
on-tim e cut
short
norm al
turn off
tim e
Program m ed delay =
8/32 PWM periods
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