參數(shù)資料
型號(hào)： TLE8242-2
廠商： INFINEON TECHNOLOGIES AG
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP64
封裝： GREEN, PLASTIC, LQFP-144
文件頁數(shù)： 13/78頁
文件大小： 1589K
代理商： TLE8242-2
TLE8242-2
Functional Description and Electrical Characteristics
Data Sheet
20
Rev. 1.0, 2010-02-09
5.3
Diagnostics
The TLE8242 includes both on-state and off-state diagnostics. On-state diagnostics are active when the OUTx pin
is driven high and off-state diagnostics are active when the OUTx pin is driven low. A detected fault can be used
to activate the open drain FAULT pin on the IC. This pin can be used to interrupt the microcontroller when a fault
is detected. Certain faults can be prevented from activating the FAULT pin by setting the fault mask register in SPI
message #1.
Once a fault is detected it is latched into the respective fault register. The microcontroller can access the fault
registers by SPI messages #4, #5, and #19.
If the RESET_B line transitions high-to-low, a RB_L bit is latched into the Generic Flag Bits register. This register
is cleared after it is read from the SPI, and the RB_L bit will not be set again until the next high-to-low transition
occurs on the RESET_B pin.
If the ENABLE pin voltage is low, the EN_L bit is latched in the Generic Flag Bits register. The ENL bit is cleared
when the ENABLE pin returns to a high state and the Generic Flag Bits register is accessed by SPI message #19.
The diagnostic delay timers for the on-state and off-state diagnostic functions are derived from the master clock
signal applied to the pin CLK using a programmable predivider. This predivider is programmable by the
DIAG_TMR bits in SPI message #1.
Three unique fault types are detected using 4 different fault bits
The fault bit is set to a “1“ if the fault is detected.
Note: In order to differentiate between a Short to Ground Failure and an Open Load Failure, the channel must be
turned off (setpoint = 0ma).
Tested Diagnostic Bits
Table 2
Timebase for Diagnostics
DIAG_TMR1
DIAG_TMR0
Pre-divider
nfault
min ... max
Tested Timer and Fault Detection
Timer Period.
fCLK=20 MHz
fCLK=40 MHz
0
128
10 ... 11
64
sec
32
sec
0
1
192
10 ... 11
96
sec
48
sec
1
0
128
2 ... 3
12.8
sec
6.4
sec
1
256
10 ... 11
128
sec
64
sec
Table 3
Diagnostic Flags / Bits
Fault Type
Abr.
Gate is ON
Gate is OFF
Short to Ground Fault
SG
OL-ON-F reported (=0 in
ON/OFF mode)
Bit SG-F
Short to Battery Fault
SB
Bit SB-F
Open Load Fault
OL
BIT OL-ON-F
(=0 in ON/OFF mode)
Bit OL-OFF-F
CLK
fault
D
DIAG_PERIO
F
predivider
*
n
t
=
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