參數(shù)資料
型號： TLIU04C1
英文描述： TLIU04C1 Quad T1/E1 Line Interface
中文描述： TLIU04C1四T1/E1線路接口
文件頁數(shù)： 54/100頁
文件大?。?/td> 1321K
代理商： TLIU04C1
Advance Data Sheet, Rev. 2
TLIU04C1 Quad T1/E1 Line Interface
April 1999
54
Lucent Technologies Inc.
Microprocessor Mode
(continued)
Microprocessor Interface Timing
(continued)
Table 37. Microprocessor Interface I/O Timing Specifications
(continued)
The read and write timing diagrams for all four microprocessor interface modes are shown in Figures 15—22.
Symbol
Configuration
Parameter
Setup
(ns)
(Min)
—
10
—
10
30
—
—
—
—
—
—
—
10
—
5
—
—
—
—
10
—
Hold
(ns)
(Min)
10
—
10
—
—
—
—
—
5
—
15
—
—
5
—
10
—
15
—
—
10
Delay
(ns)
(Max)
—
—
—
—
—
20
25
50
—
20
—
10
—
—
—
—
20
—
25
—
—
t23
t24
t25
t26
t27
t28
t29
t30
t31
t32
t33
t34
t35
t36
t37
t38
t39
t40
t41
t42
t43
Modes 3 and 4
ALE Asserted Width
Address Valid to ALE Asserted
ALE Asserted to Address Invalid
CS Asserted to ALE Asserted
ALE Asserted to RD Asserted
CS Asserted to RDY Low
Falling Edge of MPCLK to RDY Asserted
RD Asserted to Data Valid
RD Deasserted to Data Invalid
RD Deasserted to RDY Deasserted
RD Deasserted to CS Deasserted
CS Deasserted to RDY High Impedance
ALE Asserted to WR Asserted
WR Asserted Width
Data Valid to WR Asserted
WR Deasserted to Data Invalid
WR Deasserted to RDY Deasserted
WR Deasserted to CS Deasserted
Rising Edge of MPCLK to RDY Asserted
Address Valid to ALE Asserted
ALE Asserted to Address Invalid
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