參數(shù)資料
型號(hào): TLV1548QDBRG4Q1
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封裝: GREEN, PLASTIC, SSOP-20
文件頁(yè)數(shù): 13/34頁(yè)
文件大小: 532K
代理商: TLV1548QDBRG4Q1
TLV1548Q1
LOW VOLTAGE 10BIT ANALOGTODIGITAL CONVERTER
WITH SERIAL CONTROL AND 8 ANALOG INPUTS
SGLS172B JUNE 2003 REVISED APRIL 2008
20
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
td(EOC↑-CS↓)
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS
↓ before responding to control input
signals. No attempt should be made to clock in input data until the minimum CS setup time elapses.
1
2
3
4
5
6
7
8
9
10
I/O CLK
Conversion
Sample
(6 I/O CLKs)
DI
DO
EOC
CS
MSB
LSB
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Hi-Z
A3
A2
A1
A0
Rise After 10th I/O CLK
(see Note A)
Address Sampled
Initialize State Machine
and Counter
Access
Conversion Starts on 10th I/O CLK
0s
A3
D9
Figure 16. Microprocessor Interface Timing (Normal Sample Mode, INV CLK = High)
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS
↓ before responding to control input
signals. No attempt should be made to clock in input data until the minimum CS setup time has elapsed.
td(EOC↑-CS↓)
1
2
3
45
6
7
89
10
I/O CLK
Conversion
Sample
DI
DO
EOC
CS
MSB
LSB
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Hi-Z
A2
A1
A0
Rise After 10th I/O CLK
(see Note A)
Address Sampled
Conversion Starts on 10th I/O CLK
Initialize State Machine
and Counter
(5.5 I/O CLKs)
Access
0s
A3
D9
A3
Figure 17. Microprocessor Interface Timing (Normal Sample Mode, INV CLK = Low)
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