參數(shù)資料
型號(hào): TLV1548QDBRG4Q1
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封裝: GREEN, PLASTIC, SSOP-20
文件頁數(shù): 6/34頁
文件大?。?/td> 532K
代理商: TLV1548QDBRG4Q1
TLV1548Q1
LOW VOLTAGE 10BIT ANALOGTODIGITAL CONVERTER
WITH SERIAL CONTROL AND 8 ANALOG INPUTS
SGLS172B JUNE 2003 REVISED APRIL 2008
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage, VCC
2.7
5.5
V
Positive reference voltage, Vref + (see Note 2)
VCC
V
Negative reference voltage, Vref (see Note 2)
0
V
Differential reference voltage, Vref + Vref (see Note 2)
2.5
VCC
VCC +0.2
V
Analog input voltage, VI (analog) (see Note 2)
0
VCC
V
High-level control input voltage, VIH
2.1
V
Low-level control input voltage, VIL
0.6
V
Setup time, input data bits valid before I/O CLK
↑↓, tsu(A) (see Figure 9)
100
ns
Hold time, input data bits valid after I/O CLK
↑↓, th(A) (see Figure 9)
5
30
ns
Setup time, CS
↓ to I/O CLK↑, tsu(CS)
See Figure 10 and Note 3
5
30
ns
Hold time, I/O CLK
↓ to CS↑, th(CS)
See Figure 10
65
ns
Pulse duration, FS high, twH(FS)
See Figure 14
1
I/O CLK
periods
Pulse duration, CSTART, tw(CSTART)
Source impedance
≤ 1 k, VCC = 5.5 V,
See Figure 15
0.84
s
Setup time, CS
↑ to CSTART↓, tsu(CSTART)
See Figure 15
10
ns
Clock frequency at I/O CLK, fCLK
VCC = 5.5 V
0.1
6
10
MHz
Clock frequency at I/O CLK, fCLK
VCC = 2.7 V
0.1
2
2.81
MHz
Pulse duration, I/O CLK high, twH(I/O)
VCC = 5.5 V
50
ns
Pulse duration, I/O CLK high, twH(I/O)
VCC = 2.7 V
100
ns
Pulse duration, I/O CLK low, twL(I/O)
VCC = 5.5 V
50
ns
Pulse duration, I/O CLK low, twL(I/O)
VCC = 2.7 V
100
ns
Operating free-air temperature, TA
TLV1548Q
40
125
°C
Junction temperature, TJ
TLV1548Q
150
°C
NOTES:
2. Analog input voltages greater than the voltage applied to REF+ convert as all ones (1111111111), while input voltages less than the
voltage applied to REF convert as all zeros (0000000000). The device is functional with reference (Vref+ Vref) down to 1 V;
however, the electrical specifications are no longer applicable.
3. To minimize errors caused by noise at CS
↓, the internal circuitry waits for a setup time after CS↓ before responding to control input
signals. No attempt should be made to clock in an input dat until the minimum CS setup time has elapsed.
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