參數資料
型號: TLV1562IDW
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
封裝: 1.27 MM PITCH, GREEN, SOIC-28
文件頁數: 10/41頁
文件大?。?/td> 600K
代理商: TLV1562IDW
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
18
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
dual continuous mode (CR0.(3,2) = 1,1)
When the TLV1562 operates in the dual continuous mode, it samples and then holds two preselected channels
(differential or single ended) simultaneously as RD clocks. These samples are then converted in sequence. This
is designed to optimize the DSP MIPS for communication applications. Its cycle time is approximately 10
SYSCLK cycles when an external SYSCLK is used (12 SYSCLK cycles when an internal SYSCLK is used).
When operating in the dual continuous mode, the TLV1562 is always sampling the input regardless of the state
of the other control signals when it is not in the hold state. This simplifies control of the ADC. There is no need
to generate any special signal to start the sampling. The TLV1562 goes into hold mode on the odd number
(starting from the rising edge of WR) falling edge of RD for one SYSCLK clock cycle.
A two-depth FIFO is used (only in the dual continuous mode) to ensure the output correlation. Thus on every
alternate RD edge, the result of the previous two conversions is read out. This allows a slower RD clock
frequency (slower than 1/5 of the SYSCLK frequency). Each dual continuous mode cycle (while CS remains
active low) must have an even number of RD cycles to ensure the FIFO operates properly.
CS
WR
RD
DATA
t dis(DATAOUT)
t en(DATAOUT)
t d(RDL-SAMPLE)
t c(RD)
t s5
tconv2
t conv2
CONV 1
CONV 2
CONV 3
t s3
Sample 2
t s3
Sample 3
t s3
Sample 4
D 1A
D 1B
D 2A
GFG
Sample 1
D 2B
VIH
VIL
Figure 15. Dual Continuous Mode
system clock source
The TLV1562 uses multiple clocks for different internal tasks. SYSCLK is used for most conversion subtasks.
The source of SYSCLK is programmable via control register 0, bit 5 (CR0.5). The source of SYSCLK is changed
at the rising edge of WR of the cycle when CR0.5 is programmed.
internal oscillator (CR0.5 = 0, SYSCLK = internal OSC)
The TLV1562 has a built-in 8-MHz oscillator. When the internal OSC is selected as the source of SYSCLK, the
internal clock starts with a delay (one half of the OSC clock period max) after the falling edge of the conversion
trigger (RD or CSTART).
相關PDF資料
PDF描述
TLV1562IPWG4 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
TLV1562CPWLE 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
TLV1562IPWLE 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
TLV1562IDWRG4 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
TLV1570CPWG4 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
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TLV1562IDWG4 功能描述:模數轉換器 - ADC 10-Bit 2 MSPS Quad Channel RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
TLV1562IDWR 功能描述:模數轉換器 - ADC 10-Bit 2 MSPS Quad Channel RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
TLV1562IDWRG4 功能描述:模數轉換器 - ADC 10-Bit 2 MSPS Quad Channel RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
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