參數(shù)資料
型號(hào): TLV2264QDG4
廠商: Texas Instruments
文件頁(yè)數(shù): 36/64頁(yè)
文件大?。?/td> 0K
描述: IC OPAMP GP R-R 710KHZ 14SOIC
標(biāo)準(zhǔn)包裝: 50
系列: LinCMOS™
放大器類(lèi)型: 通用
電路數(shù): 4
輸出類(lèi)型: 滿擺幅
轉(zhuǎn)換速率: 0.55 V/µs
增益帶寬積: 710kHz
電流 - 輸入偏壓: 1pA
電壓 - 輸入偏移: 300µV
電流 - 電源: 800µA
電流 - 輸出 / 通道: 50mA
電壓 - 電源,單路/雙路(±): 2.7 V ~ 8 V,±1.35 V ~ 4 V
工作溫度: -40°C ~ 125°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 14-SOIC
包裝: 管件
TLV226x, TLV226xA
Advanced LinCMOS RAILTORAIL
OPERATIONAL AMPLIFIERS
SLOS186C FEBRUARY 1997 REVISED AUGUST 2006
41
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts
, the model generation software used
with Microsim PSpice
. The Boyle macromodel (see Note 5) and subcircuit in Figure 62 are generated using
the TLV226x typical electrical and operating characteristics at TA = 25°C. Using this information, output
simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
D Maximum positive output voltage swing
D Maximum negative output voltage swing
D Slew rate
D Quiescent power dissipation
D Input bias current
D Open-loop voltage amplification
D Unity-gain frequency
D Common-mode rejection ratio
D Phase margin
D DC output resistance
D AC output resistance
D Short-circuit output current limit
NOTE 5: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Intergrated Circuit Operational Amplifiers,” IEEE
Journal of Solid-State Circuits, SC-9, 353 (1974).
OUT
+
+
+
+
+
+
+
+
+
.SUBCKT TLV226x 1 2 3 4 5
C1
11
12
5.5E12
C2
6
7
20.00E12
DC
5
53
DX
DE
54
5
DX
DLP
90
91
DX
DLN
92
90
DX
DP
43DX
EGND
99
0
POLY (2) (3,0) (4,0) 0 .5 .5
FB
7
99
POLY (5) VB VC VE VLP
+ VLN 0 8.84E6 10E6 10E6 10E6 10E6
GA
6
0
11
12 62.83E6
GCM
0
6
10
99 12.34E9
ISS
3
10
DC 11.05E6
HLIM
90
0
VLIM 1K
J1
11
2
10 JX
J2
12
1
10 JX
R2
6
9
100.0E3
RD1
60
11
15.92E3
RD2
60
12
15.92E3
R01
8
5
135
R02
7
99
135
RP
3
4
15.87E3
RSS
10
99
18.18E6
VAD
60
4
.5
VB
9
0
DC 0
VC
3
53
DC .615
VE
54
4
DC .615
VLIM
7
8
DC 0
VLP
91
0
DC 1
VLN
0
92
DC 5.1
.MODEL DX D (IS=800.0E18)
.MODEL JX PJF (IS=500.0E15 BETA=325E6
+ VTO=.08)
.ENDS
VCC +
RP
IN
2
IN +
1
VCC
VAD
RD1
11
J1
J2
10
RSS
ISS
3
12
RD2
60
VE
54
DE
DP
VC
DC
4
C1
53
R2
6
9
EGND
VB
FB
C2
GCM
GA
VLIM
8
5
RO1
RO2
HLIM
90
DLP
91
DLN
92
VLN
VLP
99
7
Figure 62. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
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