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參數(shù)資料
| 型號： | TLV2548QDWG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | PLASTIC, SOIC-20 |
| 文件頁數(shù)： | 11/43頁 |
| 文件大小： | 989K |
| 代理商： | TLV2548QDWG4 |
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TLV2544Q, TLV2548Q, TLV2548M
3V TO 5.5V, 12BIT, 200KSPS, 4/8CHANNEL, LOW POWER
SERIAL ANALOGTODIGITAL CONVERTERS WITH AUTOPOWERDOWN
SGLS119F FEBRUARY 2002 REVISED OCTOBER 2009
19
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
reference block equivalent circuit
INT REF
Close = Int Ref Used
Open = Ext Ref Used
REFM
Sample
Convert
~50 pF
CDAC
External to the Device
10
F
Internal
Reference
Compensation
Cap
0.1
F
Decoupling
Cap
REFP
NOTES: A. If internal reference is used, tie REFM to AGND and install a 10
F (or 4.7 F) internal reference compensation capacitor between
REFP and REFM to store the charge as shown in the figure above.
B. If external reference is used, the 10
F (internal reference compensation) capacitor is optional. REFM can be connected to external
REFM or AGND.
C. Internal reference voltage drift, due to temperature variations, is approximately
±10 mV about the nominal 2 V (typically) from 10°C
to 100
°C . The nominal value also varies approximately ±50 mV across devices.
D. Internal reference leakage during low ON time: Leakage resistance is on the order of 100 M
or more. This means the time constant
is about 1000 s with 10
F compensation capacitance. Since the REF voltage does not vary much, the reference will come up quickly
after resuming from auto power down. At power up and power down the internal reference sees a glitch of about 500
V when 2
V internal reference is used (1 mV when 4 V internal reference is used). This glitch settles out after about 50
s.
power down
Writing 8000h to the device puts the device into a software power down state. For a hardware power-down, the
dedicated PWDN pin provides another way to power down the device asynchronously. These two power-down
modes power down the entire device including the built-in reference to save power. It requires 20 ms to resume
from either a software or hardware power down.
Auto power-down mode is always enabled. This mode maintains the built-in reference if an internal reference
is used so resumption is fast enough to be used between cycles.
The configuration register is not affected by any of the power down modes but the sweep operation sequence
has to be started over again. All FIFO contents are cleared by the power-down modes.
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| TLV2548QDWRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Auto Cat 12B 200 kSPS ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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| TLV2553EVM-PDK | 功能描述:TLV2553 - 12 Bit 200k Samples per Second Analog to Digital Converter (ADC) Evaluation Board 制造商:texas instruments 系列:- 零件狀態(tài):有效 A/D 轉(zhuǎn)換器數(shù):1 位數(shù):12 采樣率（每秒）:200k 數(shù)據(jù)接口:SPI 輸入范圍:0 ~ VREF 不同條件下的功率（典型值）:- 使用的 IC/零件:TLV2553 所含物品:板 標(biāo)準(zhǔn)包裝:1 |
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