參數(shù)資料
型號： TLV2548QDWG4
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封裝： PLASTIC, SOIC-20
文件頁數(shù)： 8/43頁
文件大?。?/td> 989K
代理商： TLV2548QDWG4
TLV2544Q, TLV2548Q, TLV2548M
3V TO 5.5V, 12BIT, 200KSPS, 4/8CHANNEL, LOW POWER
SERIAL ANALOGTODIGITAL CONVERTERS WITH AUTOPOWERDOWN
SGLS119F FEBRUARY 2002 REVISED OCTOBER 2009
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
modes using the FIFO: modes 01, 10, 11 timing (continued)
CS
CSTART
SDI
INT
SDO
Hi-Z
FS
(DSP)
Configure
Select
Conversion #1 From Channel 2
Select
Conversion #4 From Channel 2
Read FIFO
First FIFO Read
§
#1
#2
#3
#4
§
t(sample)
Hi-Z
Sample Times
≥ MIN t(sample)
(See Operating Characteristics)
t(sample)
Command = Configure write for mode 01, FIFO threshold = 1/2
Command = Read FIFO, 1st FIFO read
§ Command = Select ch2.
Minimum CS low time for select cycle is 6 SCLKs. The same amount of time is required between FS low to CSTART for proper channel decoding.
The low time of CSTART, not overlapped with CS low time, is the valid sampling time for the select cycle (see Figure 18).
Figure 11. TLV2544/TLV2548 Mode 01
p/DSP Serial Interface (Conversions Triggered by CSTART)
CS
CSTART
SDI
INT
SDO
From Channel 0
FS
(DSP)
From Channel 3
Configure
Conversion
Read FIFO
#1
#2
#3
#4
Top of FIFO
Read FIFO
#1
From Channel 0
Conversion
From Channel 3
Conversion
Repeat
Second FIFO Read
Repeat
First FIFO Read
§
§
Command = Configure write for mode 10 or 11, FIFO threshold = 1/2, sweep seq = 0123.
Command = Read FIFO
§ Use any channel select command to trigger SDI input.
Figure 12. TLV2544/TLV2548 Mode 10/11 DSP Serial Interface (Conversions Triggered by FS)
相關PDF資料
PDF描述
5962-9957001QRA 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP20
TLV2548MJ 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP20
5962-9957601Q2A SERIAL INPUT LOADING, 3.5 us SETTLING TIME, 12-BIT DAC, CQCC20
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