參數(shù)資料
型號: TLV2771QDBVRQ1
廠商: TEXAS INSTRUMENTS INC
元件分類: 運(yùn)算放大器
英文描述: OP-AMP, 2700 uV OFFSET-MAX, 4.8 MHz BAND WIDTH, PDSO5
封裝: PLASTIC, SOT-23, 5 PIN
文件頁數(shù): 30/45頁
文件大?。?/td> 986K
代理商: TLV2771QDBVRQ1
TLV277x-Q1, TLV277xA-Q1
FAMILY OF 2.7-V HIGH-SLEW-RATE RAIL-TO-RAIL OUTPUT
OPERATIONAL AMPLIFIERS WITH SHUTDOWN
SGLS179D SEPTEMBER 2003 REVISED AUGUST 2008
36
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts
Release 8, the model generation
software used with Microsim PSpice
. The Boyle macromodel (see Note 4) and subcircuit in Figure 64 are
generated using the TLV2772 typical electrical and operating characteristics at TA = 25°C. Using this
information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most
cases):
D Maximum positive output voltage swing
D Maximum negative output voltage swing
D Slew rate
D Quiescent power dissipation
D Input bias current
D Open-loop voltage amplification
D Unity-gain frequency
D Common-mode rejection ratio
D Phase margin
D DC output resistance
D AC output resistance
D Short-circuit output current limit
NOTE 6: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
OUT
+
+
+
+
+
+
+
+
VDD +
rp
IN
2
IN+
1
GND
rd1
11
j1
j2
10
rss
iss
3
12
rd2
ve
54
de
dp
vc
dc
4
C1
53
r2
6
9
egnd
vb
fb
C2
gcm
ga
vlim
8
5
ro1
ro2
hlim
90
dlp
91
dln
92
vln
vlp
99
7
css
* TLV2772 operational amplifier macromodel subcircuit
* created using Parts release 8.0 on 12/12/97 at 10:08
* Parts is a MicroSim product.
*
* connections: noninverting input
*
| inverting input
*
| | positive power supply
*
| | | negative power supply
*
| | | | output
*
| | | | |
.subckt TLV2772
1 2 3 4 5
*
c1
11
12
2.8868E-12
c2
6
7
10.000E12
css
10
99
2.6302E12
dc
5
53
dy
de
54
5
dy
dlp
90
91
dx
dln
92
90
dx
dp
4
3
dx
egnd
99
0
poly(2) (3,0) (4,0) 0 .5 .5
fb
7
99
poly(5) vb vc ve vlp vln 0
15.513E6 1E3 1E3 16E6 16E6
ga
6
0
11 12 188.50E6
gcm
0
6
10 99 9.4472E9
iss
3
10
dc
145.50E6
hlim
90
0
vlim 1K
j1
11
2
10 jx1
j2
12
1
10 jx2
r2
6
9
100.00E3
rd1
4
11
5.3052E3
rd2
4
12
5.3052E3
ro1
8
5
17.140
ro2
7
99
17.140
rp
3
4
4.5455E3
rss
10
99
1.3746E6
vb
9
0
dc 0
vc
3
53
dc .82001
ve
54
4
dc .82001
vlim
7
8
dc 0
vlp
91
0
dc 47
vln
0
92
dc 47
.model
dx
D(Is=800.00E18)
.model
dy
D(Is=800.00E18 Rs=1m Cjo=10p)
.model
jx1
PJF(Is=2.2500E12 Beta=244.20E6
+ Vto=.99765)
.model
jx2
PJF(Is=1.7500E12 Beta=244.20E6
+ Vto=1.002350)
.ends
*$
Figure 64. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
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