參數(shù)資料
型號(hào)： TLV320ADC3101IRGER320
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQCC24
封裝： 4 X 4 MM, GREEN, PLASTIC, VQFN-24
文件頁(yè)數(shù)： 13/83頁(yè)
文件大?。?/td> 1338K
代理商： TLV320ADC3101IRGER320
LD (n)
LD(n+1)
2
1
0
3
2
1
0
3
RD (n)
WORD
CLOCK
BIT
CLOCK
DATA
n-1 n-2 n-3
Left Channel
Right Channel
Ch_Offset_1 = 0
Ch_Offset_2 = 1
RD(n)
RD(n+1)
2
1
0
3
2
1
0
3
LD (n)
WORD
CLOCK
BIT
CLOCK
DATA
n-1 n-2 n-3
Right Channel
Left Channel
Ch_Offset_1 = 0
Ch_Offset_2 = 1
I2S Mode
SLAS553A – NOVEMBER 2008 – REVISED SEPTEMBER 2009...................................................................................................................................... www.ti.com
When time-based-slot mode is enabled with no channel swapping, the MSB of the left channel is valid on the
(Offset1 + 1)th rising edge of the bit clock following the rising edge of the word clock. And, the MSB of the right
channel is valid on the (Ch_Offset_2 + 1)th rising edge of the bit clock following the LSB of the left channel.
Figure 21 shows the operation with time-based-slot mode enabled and Ch_Offset_1 = 0 and Ch_Offset_2 = 1.
The MSB of the left channel is valid on the first rising edge of the bit clock after the rising edge of the word clock.
Data transfer for the right channel does not wait for the falling edge of the word clock, and the MSB of the right
channel is valid on the second rising edge of the bit clock after the LSB of the left channel.
Figure 21. Left-Justified Mode, Time-Based-Slot Mode Enabled, Ch_Offset_1 = 0, Ch_Offset_2 = 1
For the case with time-based-slot mode enabled and channel swapping enabled, the MSB of the right channel is
valid on the (Ch_Offset_1 + 1)th rising edge of the bit clock following the rising edge of the word clock. And, the
MSB of the left channel is valid on the (Ch_Offset_2 + 1)th rising edge of the bit clock following the LSB of the
right channel. Figure 22 shows the operation in this mode with Ch_Offset_1 = 0 and Ch_Offset_2 = 1. The MSB
of the right channel is valid on the first rising edge of the bit clock after the rising edge of the word clock. Data
transfer for the left channel starts following the completion of data transfer for the right channel without waiting for
the falling edge of the word clock. The MSB of the left channel is valid on the second rising edge of the bit clock
after the LSB of the right channel.
Figure 22. Left-Justified Mode, Time-Based-Slot Mode Enabled, Ch_Offset_1 = 0, Ch_Offset_2 = 1,
Channel Swapping Enabled
In I2S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge
of the word clock. Similarly, the MSB of the right channel is valid on the second rising edge of the bit clock after
the rising edge of the word clock. Figure 23 shows the standard I2S timing.
20
Copyright 2008–2009, Texas Instruments Incorporated
Product Folder Link(s) :TLV320ADC3101
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TLV320AIC10C 制造商:TI 制造商全稱:Texas Instruments 功能描述:General-Purpose 3V to 5.5V 16-bit 22-KSPS DSP CODEC
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