參數(shù)資料
型號： TLV320AIC26IRHB
廠商： Texas Instruments, Inc.
元件分類： Codec
英文描述： LOW POWER STEREO AUDIO CODEC WITH HEADPHONE/SPEAKER AMPLIFIER AND 12-BIT BATTERY / TEMPERATURE / AUXILIARY ADC
中文描述： 低功耗立體聲音頻編解碼器耳機/揚聲器放大器和12位電池/溫度/輔助ADC
文件頁數(shù)： 32/74頁
文件大小： 896K
代理商： TLV320AIC26IRHB
TLV320AIC26
SLAS412 DECEMBER 2003
www.ti.com
38
REGISTER 01H: Status Register
BIT
NAME
READ/
WRITE
RESET
VALUE
FUNCTION
D15D14
DAV
R/W
10
Data Available. These two bits program the function of the DAV pin.
00 => Reserved
01 => Acts as data available (Active Low) only. The DAV goes low as soon as one set of ADC
conversion is completed. For scan mode, DAV remains low as long as all the appropriate
registers have not been read out.
10 => Reserved
11 => Reserved
Note: D15D14 should be programmed to 01 for the ’AIC26 to operate correctly.
D13
PWRDN
R
0
AUXADC Power down status
0 => AUXADC is active
1 => AUXADC stops conversion and powers down
D12
R
0
Reserved
D11
DAVAIL
R
0
Data Available Status
0 => No data available.
1 => Data is available(i.e., one set of conversion is done).
Note: This bit is cleared only after all the converted data has been completely read out.
D10D7
R
0000
Reserved
D6
B1STAT
R
0
BAT1 Data Register Status
0 => No new data is available in BAT1 data register
1 => New data is available in BAT1 data register
Note: This bit is cleared only after the converted data of BAT1 has been completely read out of the
register.
D5
B2STAT
R
0
BAT2 Data Register Status
0 => No new data is available in BAT2 data register
1 => New data is available in BAT2 data register
Note: This bit is cleared only after the converted data of BAT2 has been completely read out of the
register.
D4
AXSTAT
R
0
AUX Data Register Status
0 => No new data is available in AUX data register
1 => New data is available in AUX data register
Note: This bit is cleared only after the converted data of AUX has been completely read out of the
register.
D3
R
0
Reserved
D2
T1STAT
R
0
TEMP1 Data Register Status
0 => No new data is available in TEMP1 data register
1 => New data is available in TEMP1 data register
Note: This bit is cleared only after the converted data of TEMP1 has been completely read out of the
register.
D1
T2STAT
R
0
TEMP2 Data Register Status
0 => No new data is available in TEMP2 data register
1 => New data is available in TEMP2 data register
Note: This bit is cleared only after the converted data of TEMP2 has been completely read out of the
register.
D0
R
0
Reserved
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