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參數(shù)資料
| 型號(hào)： | TLV320AIC27CPFB |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, TQFP-48 |
| 文件頁數(shù)： | 32/54頁 |
| 文件大?。?/td> | 732K |
| 代理商： | TLV320AIC27CPFB |
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TLV320AIC27
STEREO AUDIO CODEC
SLAS253A – MARCH 2000 – REVISED SEPTEMBER 2000
38
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operational mode description
operational modes
The TLV320AIC27 has four modes of operation: two-channel, six-channel I2S, quad, and modem. The mode
is determined by pins 30 and 40, as shown in Table 21.
Table 21. Modes of Operation
MODE1
(MODE40)
MODE0
(PIN30)
OPERATIONAL
MODE
RESULTING DEVICE BEHAVIOR
0
Basic
Two-channel mode codec
0
1
Six-channel I2S
Six-channel mode codec
1
0
Quad
Quad DAC mode (with I2S six-channel support)
1
Modem
Modem DAC mode
basic mode
In basic mode, the TLV320AIC27 comprises a stereo 18-bit codec, (that is, two ADCs and two DACs) plus a
comprehensive analog mixer with four sets of stereo inputs, plus one phone input, two microphone inputs, and
one PC-beep input. The TLV320AIC27 supports 18-bit resolution within the DAC and ADC functions. However,
the AC’97 serial interface specification allows any word length up to 20-bits to be written to, or read from the
AC’97 codec. These words are MSB-justified, and any unused LSBs simply defaults to 0. It is anticipated that
16-bit words will be used in most applications. Therefore, for the DAC, 16-bit words will be downloaded into the
codec from the controller, along with padding of 0s to make the 16-bit word up to 20-bit in length. In this case,
the TLV320AIC27 processes the 16-bit word along with 0 padding bits in the two LSB locations (to make it
18-bit). At the ADC output, the TLV320AIC27 provides an 18-bit word, again with 0s in the two LSB locations
(20-bit). The AC’97 controller then ignores the four LSBs of the 20-bit word. When the TLV320AIC27 is
interrogated, its response indicates it is an 18-bit device.
An internally generated midrail reference is provided at pin CAP2 which is used as the chip reference. This pin
should be heavily decoupled.
basic mode features
D Vendor ID reads back as TXN3
D Two channels of ADC and DAC conversion provided, with all recommended audio and modem sample rates
supported via the audio sample-rate registers 2Ch and 32h
D Master/slave ID0/1 supported
D Headphone/line level outputs (duplicating the main outputs) supported, with gain control from register 04h
D 3D stereo enhanced sound supported
D Master volume control register maps to the location dependant on selected ID: (ID 00 or 01 uses master
volume at register 02h, ID 10 uses 38h (surround volume), and ID 11 uses 36h (LFE, center volume)
quad mode
The TLV320AIC27 codec comprises two channels of ADC and four channels of DAC. This enables a
four-channel surround sound solution to be implemented (quad mode). A symmetric mixer is provided which
allows analog signals such as CD inputs to be mixed into both front and rear channel paths simultaneously.
Alternatively, the device can be configured in six-channel I2S mode. In this mode the device uses three GPIO
pins to output rear channel and center and LFE data in I2S format to an external DAC to build a full six-channel
surround sound solution.
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