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參數(shù)資料
| 型號： | TLV320AIC28RGZR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC48 |
| 封裝： | 7 X 7 MM, PLASTIC, QFN-48 |
| 文件頁數(shù)： | 33/85頁 |
| 文件大?。?/td> | 1053K |
| 代理商： | TLV320AIC28RGZR |
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TLV320AIC28
SLAS418B FEBRUARY 2004 REVISED MAY 2005
www.ti.com
39
The user can select the input or input sequence, which needs to be converted, from the ADCSM bits of control
register 00H/page 1. The converted values are written in a predefined sequence to the circular buffer. The user
has flexibility to program a specific trigger level in order to choose the configuration which best fits the
application. When the number of converted data, written in FIFO, becomes equal to the programmed trigger
level then the device generates an interrupt signal on DAV pin.
Buffer mode can be used in single-shot conversion or continuous conversion mode.
In single shot conversion mode, once the number of data written reaches programmed trigger level, the AIC28
generates an interrupt and waits for the user to start reading. As soon as the user starts reading the first data
from the last converted set, the AIC28 clears the interrupt and starts a new set of conversions and the trigger
pointer is incremented by the programmed trigger level. An interrupt is generated again when the trigger
condition is satisfied.
In continuous conversion mode, once number of data written reaches the programmed trigger level, the AIC28
generates an interrupt. It immediately starts a new set of conversions and the trigger pointer is incremented
by the programmed trigger level. An interrupt gets cleared either by writing the next converted data into the FIFO
or by starting to read from the FIFO.
See the section Conversion Time Calculation for the AIC28 and subsection Buffer Mode Operation in this data
sheet for timing diagrams and conversion time calculations.
Depending upon how the user is reading data, the FIFO can become empty or full. If the user is trying to read
data even if the FIFO is empty, then RDPTR keeps pointing to same location. If the FIFO gets full then the next
location is overwritten with newly converted data and the read pointer is incremented by one.
While reading the FIFO, the AIC28 provides FIFO empty and full status flags along with the data. The user can
also read a status flag from control register 02H/page 1.
DIGITAL INTERFACE
RESET
The device requires reset after power up. This requires a low-to-high transition on the RESET pin after power
up for correct operation. Reset initializes all the internal registers, counters and logic.
Hardware Power-Down
Hardware power-down powers down all the internal circuitry to save power. All the register contents are
maintained.
General Purpose I/O
The AIC28 has two general purpose I/O (GPIO1 and GPIO2), which can be programmed either as inputs or
outputs. As outputs they can be programmed to control external logic through the AIC28 registers or send
interrupts to the host processor on events like button detect, headset insertion, headset removal,
Auxiliary/temperature outside threshold range etc. As inputs they can be used by the host-processor to monitor
logic states of signals on the system through the AIC28 registers.
SPI Digital Interface
All AIC28 control registers are programmed through a standard SPI bus. The SPI allows full-duplex,
synchronous, serial communication between a host processor (the master) and peripheral devices (slaves).
The SPI master generates the synchronizing clock and initiates transmissions. The SPI slave devices depend
on a master to start and synchronize transmissions.
A transmission begins when initiated by a master SPI. The byte from the master SPI begins shifting in on the
slave MOSI pin under the control of the master serial clock. As the byte shifts in on the MOSI pin, a byte shifts
out on the MISO pin to the master shift register.
The idle state of the serial clock for the AIC28 is low, which corresponds to a clock polarity setting of 0 (typical
microprocessor SPI control bit CPOL = 0). The AIC28 interface is designed so that with a clock phase bit setting
of 1 (typical microprocessor SPI control bit CPHA = 1), the master begins driving its MOSI pin and the slave
begins driving its MISO pin on the first serial clock edge. The SS pin can remain low between transmissions;
however, the AIC28 only interprets command words which are transmitted after the falling edge of SS.
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