參數(shù)資料
型號(hào): TLV320AIC3107IYZFT
廠商: TEXAS INSTRUMENTS INC
元件分類(lèi): 音頻/視頻放大
英文描述: 2 CHANNEL, AUDIO AMPLIFIER, BGA42
封裝: 3.50 X 3 MM, 0.50 MM PITCH, GREEN, DSBGA-42
文件頁(yè)數(shù): 49/99頁(yè)
文件大?。?/td> 1474K
代理商: TLV320AIC3107IYZFT
www.ti.com .............................................................................................................................................. SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009
Page 0 / Register 14:
Headset / Button Press Detection Register B
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
Driver Capacitive Coupling
0: Programs high-power outputs for capless driver configuration
1: Programs high-power outputs for ac-coupled driver configuration
D6(1)
R/W
0
Stereo Output Driver Configuration A
Note: do not set bits D6 and D3 both high at the same time.
0: A stereo fully-differential output configuration is not being used
1: A stereo fully-differential output configuration is being used
D5
R
0
Button Press Detection Flag
This register is a sticky bit, and will stay set to 1 after a button press has been detected, until the
register is read. Upon reading this register, the bit is reset to zero.
0: A button press has not been detected
1: A button press has been detected
D4
R
0
Headset Detection Flag
0: A headset has not been detected
1: A headset has been detected
D3(1)
R/W
0
Stereo Output Driver Configuration B
Note: do not set bits D6 and D3 both high at the same time.
0: A stereo pseudo-differential output configuration is not being used
1: A stereo pseudo-differential output configuration is being used
D2–D0
R
000
Reserved. Write only zeros to these bits.
(1)
Do not set D6 and D3 to 1 simultaneously
Page 0 / Register 15:
Left ADC PGA Gain Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
1
Left ADC PGA Mute
0: The left ADC PGA is not muted
1: The left ADC PGA is muted
D6-D0
R/W
0000000
Left ADC PGA Gain Setting
0000000: Gain = 0.0 dB
0000001: Gain = 0.5 dB 0000010: Gain = 1.0 dB
1110110: Gain = 59.0 dB
1110111: Gain = 59.5 dB
1111000: Gain = 59.5 dB
1111111: Gain = 59.5 dB
Page 0 / Register 16:
Right ADC PGA Gain Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
1
Right ADC PGA Mute
0: The right ADC PGA is not muted
1: The right ADC PGA is muted
D6-D0
R/W
0000000
Right ADC PGA Gain Setting
0000000: Gain = 0.0 dB
0000001: Gain = 0.5 dB
0000010: Gain = 1.0 dB
1110110: Gain = 59.0 dB
1110111: Gain = 59.5 dB
1111000: Gain = 59.5 dB
1111111: Gain = 59.5 dB
Copyright 2008–2009, Texas Instruments Incorporated
53
Product Folder Link(s): TLV320AIC3107
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