參數(shù)資料
型號： TLV320AIC3107IYZFT
廠商： TEXAS INSTRUMENTS INC
元件分類： 音頻／視頻放大
英文描述： 2 CHANNEL, AUDIO AMPLIFIER, BGA42
封裝： 3.50 X 3 MM, 0.50 MM PITCH, GREEN, DSBGA-42
文件頁數(shù)： 52/99頁
文件大?。?/td> 1474K
代理商： TLV320AIC3107IYZFT
SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 .............................................................................................................................................. www.ti.com
Page 0 / Register 21:
LINE1R to Left ADC Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
LINE1R Single-Ended vs Fully Differential Control
If LINE1R is selected to both left and right ADC channels, both connections must use the same
configuration (single-ended or fully differential mode).
0: LINE1R is configured in single-ended mode
1: LINE1R is configured in fully differential mode
D6–D3
R/W
1111
LINE1R Input Level Control for Left ADC PGA Mix
Setting the input level control to a gain below automatically connects LINE1R to the left ADC
PGA mix
0000: Input level control gain = 0.0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3.0 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6.0 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9.0 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12.0 dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: LINE1R is not connected to the left ADC PGA
D2–D0
R
000
Reserved. Write only zeros to these register bits.
Page 0 / Register 22:
LINE1R to Right ADC Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
LINE1R Single-Ended vs Fully Differential Control
If LINE1R is selected to both left and right ADC channels, both connections must use the same
configuration (single-ended or fully differential mode).
0: LINE1R is configured in single-ended mode
1: LINE1R is configured in fully differential mode
D6–D3
R/W
1111
LINE1R Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects LINE1R to the right ADC
PGA mix
0000: Input level control gain = 0.0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3.0 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6.0 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9.0 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12.0 dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: LINE1R is not connected to the right ADC PGA
D2
R/W
0
Right ADC Channel Power Control
0: Right ADC channel is powered down
1: Right ADC channel is powered up
D1–D0
R/W
00
Right ADC PGA Soft-Stepping Control
00: Right ADC PGA soft-stepping at once per Fs
01: Right ADC PGA soft-stepping at once per two Fs
10-11: Right ADC PGA soft-stepping is disabled
56
Copyright 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC3107
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