參數(shù)資料
型號(hào)： TLV320AIC31IRHBRG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQCC32
封裝： 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁(yè)數(shù)： 37/83頁(yè)
文件大?。?/td> 1197K
代理商： TLV320AIC31IRHBRG4
SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com
Page 0 / Register 10:
Audio Serial Data Interface Control Register C
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
00000000
Audio Serial Data Word Offset Control
This register determines where valid data are placed or expected in each frame, by controlling
the offset from beginning of the frame where valid data begins. The offset is measured from
the rising edge of word clock when in DSP mode. Note: In continuous transfer mode, the
maximum offset is 17 for I2S/LJF/RJF modes and 16 for DSP mode. In 256-clock mode, the
maximum offset is 241 for DSP modes.
00000000: Data offset = 0 bit clocks
00000001: Data offset = 1 bit clock
00000010: Data offset = 2 bit clocks
…
11110001: Data offset = 241 bit clocks.
11110010: Data offset = 242 bit clocks
11110011-11111111: Reserved. Do not write these values to this register.
Page 0 / Register 11:
Audio Codec Overflow Flag Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R
0
Left ADC Overflow Flag
This is a sticky bit, so will stay set if an overflow occurs, even if the overflow condition is
removed. The register bit reset to '0' after it is read.
0: No overflow has occurred
1: An overflow has occurred
D6
R
0
Right ADC Overflow Flag
This is a sticky bit, so will stay set if an overflow occurs, even if the overflow condition is
removed. The register bit reset to '0' after it is read.
0: No overflow has occurred
1: An overflow has occurred
D5
R
0
Left DAC Overflow Flag
This is a sticky bit, so will stay set if an overflow occurs, even if the overflow condition is
removed. The register bit reset to '0' after it is read.
0: No overflow has occurred
1: An overflow has occurred
D4
R
0
Right DAC Overflow Flag
This is a sticky bit, so will stay set if an overflow occurs, even if the overflow condition is
removed. The register bit reset to '0' after it is read.
0: No overflow has occurred
1: An overflow has occurred
D3–D0
R/W
0001
PLL R Value
0000: R = 16
0001 : R = 1
0010 : R = 2
0011 : R = 3
0100 : R = 4
…
1110: R = 14
1111: R = 15
42
Copyright 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC31
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