參數(shù)資料
型號(hào)： TLV320DAC26IRHBRG4
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： SERIAL INPUT LOADING, DAC WITH PROGRAMMABLE PLL, PQCC32
封裝： 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁(yè)數(shù)： 27/52頁(yè)
文件大小： 872K
代理商： TLV320DAC26IRHBRG4
TLV320DAC26
SLAS428 AUGUST 2004
www.ti.com
33
REGISTER 06H: Audio Control 3
BIT
NAME
READ/
WRITE
RESET
VALUE
FUNCTION
D15D14
DMSVOL
R/W
00
DAC Channel Master Volume Control
00 => Left channel and right channel have independent volume controls
01 => Left channel volume control is the programmed value of the right channel volume control.
10 => Right channel volume control is the programmed value of the left channel volume control.
11 => same as 00
D13
REFFS
R/W
0
Reference Sampling Rate. This setting controls the coefficients in the de-emphasis filter. If an
Fsref above 48 kHz is being used, then it is recommended to set this to the 48-kHz setting,
otherwise either setting can be used.
0 => Fsref = 48.0 kHz
1 => Fsref = 44.1 kHz
D12
DAXFM
R/W
0
Master Transfer Mode
0 => Continuous data transfer mode
1 => 256s data transfer mode
D11
SLVMS
R/W
0
DAC Master Slave Control
0 => ’DAC26 is slave
1 => ’DAC26 is master
D10D9
DAPK2PK
R/W
00
DAC Max Output Signal Swing and Common Mode Voltage
00 => DAC max output signal swing = 2.0 V, VCM = 1.35 V
01 => DAC max output signal swing = 2.192 V (only recommended for analog supply of 3.0 V
and digital supply of 1.65 V and above), VCM = 1.48 V
10 => DAC max output signal swing = 2.402 V (only recommended for analog supply of 3.3 V
and digital supply of 1.8 V and above), VCM = 1.62 V
11 => DAC max output signal swing = 2.633 V (only recommended for analog supply of 3.6 V
and digital supply of 1.95 V), VCM = 1.78 V
D8
Reserved
R/W
0
Reserved
D7
DALOVF
R
0
DAC Left Channel Overflow Flag ( Read Only )
0 => DAC left channel data is within saturation limits.
1 => DAC left channel data has exceeded saturation limits.
Note : This flag is reset only on register read.
D6
DAROVF
R
0
DAC Right Channel Overflow Flag ( Read Only )
0 => DAC right channel data is within saturation limits.
1 => DAC right channel data has exceeded saturation limits.
Note : This flag is reset only on register read.
D5D0
Reserved
R/W
0
Reserved
Note: Always write the reset value to this bit
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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