參數(shù)資料
型號(hào)： TLV320DAC26IRHBRG4
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： DAC
英文描述： SERIAL INPUT LOADING, DAC WITH PROGRAMMABLE PLL, PQCC32
封裝： 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁(yè)數(shù)： 51/52頁(yè)
文件大?。?/td> 872K
代理商： TLV320DAC26IRHBRG4
TLV320DAC26
SLAS428 AUGUST 2004
www.ti.com
8
AUDIO INTERFACE TIMING DIAGRAMS
LRCK/ADWS
BCLK
DIN
td(WS)
ts(DI)
th(DI)
Figure 1. I2S/LJF/RJF Timing in Master Mode
TYPICAL TIMING REQUIREMENTS (FIGURE 1)
All specifications at 25
°C, DVDD = 1.8 V (1)
PARAMETER
IOVDD = 1.1 V
IOVDD = 3.3 V
UNITS
PARAMETER
MIN
MAX
MIN
MAX
UNITS
td(WS)
LRCK delay time
25
15
ns
ts(DI)
DIN setup time
6
ns
th(DI)
DIN hold time
6
ns
tr
Rise time
10
6
ns
tf
Fall time
10
6
ns
(1) These parameters are based on characterization and are not tested in production.
LRCK/ADWS
BCLK
DIN
td(WS)
ts(DI)
th(DI)
td(WS)
Figure 2. DSP Timing in Master Mode
TYPICAL TIMING REQUIREMENTS (FIGURE 2)
All specifications at 25
°C, DVDD = 1.8 V(1)
PARAMETER
IOVDD = 1.1 V
IOVDD = 3.3 V
UNITS
PARAMETER
MIN
MAX
MIN
MAX
UNITS
td(WS)
LRCK delay time
25
15
ns
ts(DI)
DIN setup time
6
ns
th(DI)
DIN hold time
6
ns
tr
Rise time
10
6
ns
tf
Fall time
10
6
ns
(1) These parameters are based on characterization and are not tested in production.
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