參數(shù)資料
型號: TLV5610IYER
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, PBGA20
封裝: WAFER CHIP SCALE, 20 PIN
文件頁數(shù): 4/17頁
文件大?。?/td> 345K
代理商: TLV5610IYER
TLV5610IYE
TLV5608IYE
SLAS393 OCTOBER 2003
www.ti.com
12
DAC AH AND TWO-CHANNEL REGISTERS
Writing to DAC AH sets the output voltage of channel AH. It is possible to automatically generate the
complement of one channel by writing to one of the four two-channel registers (DAC A and B etc.).
The TLV5610IYE decodes all 12 data bits. The TLV5608IYE decodes D11 to D2 (D1 and D0 are ignored).
PRESET
The outputs of all DAC channels can be driven to a predefined value stored in the preset register by driving the
PRE input low. The PRE input is asynchronous to the clock.
CTRL0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
PD
DO
X
IM
PD
: Full device power down
0 = normal
1 = power down
DO
: Digital output enable
0 = disable
1 = enable
IM
: Input mode
0 = straight binary
1 = twos complement
X
: Reserved
If DOUT is enabled, the data input on DIN is output on DOUT with a 16 cycle delay. That makes it possible to
daisy-chain multiple DACs on one serial bus.
CTRL1
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
PGH
PEF
PCD
PAB
SGH
SEF
SCD
SAB
PXY
: Power Down DACXY
0 = normal
1 = power down
SXY
: Speed DACXY
0 = slow
1 = fast
XY
: DAC pair AB, CD, EF or GH
In power-down mode, the amplifiers of the selected DAC pair within the device are disabled and the total power
consumption of the device is significantly reduced. Power-down mode of a specific DAC pair can be selected
by setting the PXY bit within the data word to 1.
There are two settling time modes: fast and slow. Fast mode of a DAC pair is selected by setting SXY to 1 and
slow mode is selected by setting SXY to 0.
相關(guān)PDF資料
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